Code is not synthesized as expected

[Altera_Forum]

Hi all, I have a code for registers configuration, in this code there is a "cpu interface" component which writes/reads to/from registers. The "cpu interface" drives a "cpu_wr" signal which is sent to a group of registers (the same signal is sent parallelly to all the registers in the group), this signal is the registers write enable. Behaviorally, this "cpu_wr" signal is routed parallelly to all the registers in the group, but the synthesis result is different- it seems that the signal goes through a chain of LUTs of some registers in the group before getting to the destination register. This unwanted synthesis causes some failing timinig paths (from the "cpu interface to the register). I believe that i can handle this failing path by defining it as a false path but i prefer to understand the reason to this synthsis before doing that, I'm not that experienced with FPGAs synthesis so the only reason i could thing of is that the "cpu_wr" signal might has a large fan out as it is connected to too many registers... any other ideas? i have attached the synthesis result and the hdl code. Thanks!

[Altera_Forum]

Say you failed timing but you think synthesis failed. Am I right? 

If it is due to fan out then you can duplicate as many registers for wr as you want.  But it is more helpful to present the problem as reported by tool.

[Altera_Forum]

--- Quote Start ---  Say you failed timing but you think synthesis failed. Am I right? If it is due to fan out then you can duplicate as many registers for wr as you want.  But it is more helpful to present the problem as reported by tool.  --- Quote End ---    Well, the Timequest timinig analyzer reports for failing path but this is just a warning, the synthesis is finished succesfully with- "Critical Warning: Timing requirements not met". My problem is not just the warning, i opened the thread in order to understant the attached synthesis for the attached code. Should i open it under another forum?

[Altera_Forum]

--- Quote Start ---  Well, the Timequest timinig analyzer reports for failing path but this is just a warning, the synthesis is finished succesfully with- "Critical Warning: Timing requirements not met". My problem is not just the warning, i opened the thread in order to understant the attached synthesis for the attached code. Should i open it under another forum?  --- Quote End ---    The post is ok for this forum. I wouldn't suspect synthesis is the cause of timing failure unless proved otherwise. So let us focus on timing reports what does it actually report? is it setup violation,hold violation and which paths (internal or io). can you also post the code for those register modules.

[Altera_Forum]

--- Quote Start ---  The post is ok for this forum. I wouldn't suspect synthesis is the cause of timing failure unless proved otherwise. So let us focus on timing reports what does it actually report? is it setup violation,hold violation and which paths (internal or io). can you also post the code for those register modules.  --- Quote End ---    O.K thnaks, The report is for setup violation, the code is attached. Hope you will be able to explain why the "write" port goes through other registers on its way to the destination register, maybe becasue it has bidirectional data port?

[Altera_Forum]

The wr signal goes to areas of logic: 

1) it goes to AND logic followed by registering data into int_Q then another register into out_Q (clked process) 2) it goes to the logic for data <= out_Q (combinatorial) then goes to unknown...  I wouldn't worry about looking into fitting result (at least your picture is too hard to see details). It is likely the second path is failing You will need to identify specifically which path is failing.  Regarding bidirectional bus, this will be converted to muxes and the paths will follow accordingly.