Comparing two ring oscillators in FPGA for RO PUF

[Altera_Forum]

Hi, 

 i'm doing a project on Ring Oscillator PUF to implement on FPGA. In my design, i have compared 2 ROs to see which RO is faster. When the first RO is faster than the second RO, the output bit will be 1 and if slower wil be 0. I have manually placed the ROs on the chip so that i'm using the same ROs everytime after compilation.   However there is a problem with the design, the output is very unstable. :(  Does anyone have any idea, how i can make sure the frequency cycle produced by the RO stable?

[Altera_Forum]

How do you determine "unstable"? 

Are you sure your design is able to compare asynchronous clocks?

[Altera_Forum]

Thank you for your reply. 

 What i meant by unstable was, when i compare both ROs the output is sometimes '1' and sometimes '0'.   For example, when tested the chip 10 times, the chip produced output '1' 6 times and '0' 4 times.   I would like the design to produced only '1' or '0' 9 times when i test it again 10 times.  I use counter to count the frequency of the RO and it is asynchronous. Does this mean that my design is able to compare asynchronous clocks?

[Altera_Forum]

What I meant is that when comparing RO clock with reference clock or both RO clocks, domain crossing techniques must be applied. 

 But the "unstable" result may be just a result of the RO output jitter.

[Altera_Forum]

I resolved my problem. It was the counter, i did not set the maximum limit. A very stupid mistake. 

 Thank for your reply. :)