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Jens
Novice
128 Views

Compile Error when using one inclock for SERDES IPs in different I/O banks

Hi,

I'm using a Arria 10AX048H4F34E3SG device for interfacing an image sensor. The serial LVDS data channels from sensor are connected to 6 I/O banks. The serial data clock is just within one I/O bank. I have 6 SERDES IPs instantiated which should use this clock as inclock. The Quartus Fitter generates this error for the channels which are not in the same I/O bank like the clock:

Error (175006): Could not find path between source IOPLL and the LVDS_CHANNEL

 

Is there any option to avoid this error?

I tried using an external PLL for the SERDES but it produces the same error.

 

Jens

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1 Reply
AminT_Intel
Employee
111 Views

Hello Jens,

 

You might get this error because LVDS IOPLL clock is driven across multiple banks in Arria 10. 

All RX channels need to be in one I/O bank and each I/O bank can support up to 24 channels for LVDS SERDES IP Core Functional Modes.

 

You can refer to page 4, 13, 31 and 37 document on this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

 

I hope this answer helps. 

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