Conf_Done stays low after programming

[Altera_Forum]

Hi, 

 I have a design on Cyclone III EP3C120F480C7 that works pretty well when the input clock frequency is low, but quits working when the frequency increases. The reason it quits working is because, on power-up, the conf_done signal will stays low after the normal programming process, which prevents the FPGA enter the user mode.   The only difference I can think of between working and not working is the input clock frequency. The frequency parameter is stored in a flash and is read on power-up to set a pll on the board to generate the input clock for the FPGA. All I did was change the value in the flash and recycle the power, then it either works or not depending on the frequency I set.  The FPGA uses this input clock to generate a fast clock (20x faster) internally. When the input frequency is set to 13-14MHz and the internal clock is therefore 260-280MHz (not a problem for Cyclone III according to the datasheet), somehow the FPGA refuse to enter into user mode.  Could anyone shed some light on this? Your help is very much appreciated.  Hua

[Altera_Forum]

Maybe not a problem for the device itself but for the core power supply on your board?

[Altera_Forum]

--- Quote Start ---  Hi,  I have a design on Cyclone III EP3C120F480C7 that works pretty well when the input clock frequency is low, but quits working when the frequency increases. The reason it quits working is because, on power-up, the conf_done signal will stays low after the normal programming process, which prevents the FPGA enter the user mode.   The only difference I can think of between working and not working is the input clock frequency. The frequency parameter is stored in a flash and is read on power-up to set a pll on the board to generate the input clock for the FPGA. All I did was change the value in the flash and recycle the power, then it either works or not depending on the frequency I set.  The FPGA uses this input clock to generate a fast clock (20x faster) internally. When the input frequency is set to 13-14MHz and the internal clock is therefore 260-280MHz (not a problem for Cyclone III according to the datasheet), somehow the FPGA refuse to enter into user mode.  Could anyone shed some light on this? Your help is very much appreciated.  Hua  --- Quote End ---    Hi Hua,  can you load the FPGA with the USB-Blaster? If yes, do see the same behhaviour ?

[Altera_Forum]

I am trying to program an EPCS4 from an Altera USB Byteblaster, in circuit. I can program the image store, but the Cyclone II C20 device doesn't release conf_done at the end of programming although nCONFIG is going high. (This is ASP not JTAG) 

What appears to be happening is that the USB-Blaster is holding the clock line low, and doesn't tri-state it after programming. The Cyclone tries to load the image but can't clock data from the EPCS4. It works fine if I manually disconnect the clock pin from the Blaster then reconnect it.  I need to keep the Blaster connected, so I'm looking at adding some electronics to disconnect the signal :-( Didn't see this on a Byteblaster II, but I don't have one to hand to investigate. It may be that the USB blaster can sink more current, or the BBII (again Altera) might tri-state the line.  Looking at the clock line with a scope shows lots of spiky, noisy clocks with very slow rise and fall times when both devices are connected.   Anyone know of a way to make the USB Blaster release the line?   Malcolm

[Altera_Forum]

Thank you all for your reply. Harald is right. My power supply was too weak. I guess when I increase the clock speed it demands even more power from the already weak supply. Here is a picture of my VCCINT. The green signal is VCCINT and the yellow signal is config_done: 

 http://img517.imageshack.us/img517/6336/work4qz1.th.png (http://img517.imageshack.us/my.php?image=work4qz1.png)http://img517.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)

[Altera_Forum]

You can try adding some larger/bulk capacitors as a work around for a better low frequency response and smaller caps for higher frequency response. Since, you cannot add additional pads, try stacking up the capacitors on top of each other. I have seen triple-stacked capacitors in the past.