A FPGA in one of my boards cannot load configuration file from EPCS64 device after power on. when I verify the EPCS64 device content with the original pof file using Quartus II Programmer software, it always failed in progress 10% . I think some bits changed in EPCS64, In which situation will the bits changed?
Can you provide little bit more information? What FPGA device are you using and Quartus II release version?
Check the supported FPGA devices for EPCS64 link below.
Plus, what you mean by 'EPCS64 device content with the original pof file'?
Are you trying to load EPCS64 device content .pof file with same device or different device?
If you're trying to load .pof file for other devices which is not originally generated from the same device, it is not advisable to use or change for other devices.
The FPGA is an EP3S device and it works well when I configured it with sof file in JTAG mode.
'EPCS64 device content with the original pof file' - I mean a failure is reported when performing verification with the pof file using Quartus II 9.1 Programmer software. so I think configuration file stored in EPCS64 have changed, and is mismatch with the pof file.
I didn't program a new POF file。
Firstly, I verified the configuration information stored in EPCS64, I found mismatch.
Then I configured the FPGA with a SOF file through JTAG, this operation wouldn't alert anything in EPCS64. When SOF configuration finished, I found FPGA works well.so I think sometihng wrong with EPCS64, not FPGA
Is this a custom FPGA board or a Altera Dev kit? Does the board have any jumpers/DIP switches for MSEL inputs to FPGA? What is the current setting for MSEL on the board/device?