Configure MAX10 CPLD using remote micro CPU

[Altera_Forum]

I would configure MAX10 CPLD using remote micro CPU. 

  As I got from the datasheet MAX10 has only JTAG setup, I mean first time MAX10 initialization.   I tried to look through the many docs and I found some cases for remote configure using UART and I2C but such cases require special boot image preloading. So it is not the case I could use for my project.  Also I searched many Altera docs but I did not find any explanation for timing, protocols and data flow that I can use for h/w configuration.  My goal is using JTAG programming download MAX10 image at power on initialization time. I think it is better to download image to only SRAM (not the flash CFM) so, as I understood, I need to send SOF file.   Please help me to understand how to convert SOF file to raw stream that I could use through JTAG interface?  Please also link me to any docs that could explain (timing, protocol, data flow) Altera JTAG programming on h/w level.

[Altera_Forum]

Quartus supports converting .sof files into .rbf (raw binary files). The .sof files are only for use with Quartus programmer. 

 However, before you get too excited, Altera don't publish details of their JTAG programming. This isn't how Altera intend you to put MAX 10 devices to use.  There are 3rd party hardware/software solutions that will allow you to program FPGA's via JTAG. So, it is possible. However, I'm not aware of any that publish how they do this or the JTAG protocol required.  Programming a device from a CPU really requires a device with a Passive Programming (PS) interface. All the other FPGA families support this - Cyclone, Stratix, Arria. I suggest you consider Cyclone. Then the solution is simple and cheaper.  If you really need MAX 10 (analogue features?) then I think you need to reconsider your requirements. If you do want to be able to update the design remotely, via a CPU, then you need to seriously consider the solutions Altera publish - the UART & I2C options you've already found. Alternatively, solve any analogue requirements another way and host it from a Cyclone device.  MAX 10 is simply not intended to be used in the way you want.  Cheers, Alex

[Altera_Forum]

Using Altera JRunner you can configure an FPGA via a micro, etc.  

For MAX10 & Arria10 devices Altera supplied Jam STAPL software.  The source codes are available, so you can edit them and include them in your Microcontroller code.  They accept .rbf file and the .rbf format could be generated by Altera Quartus. Have a look at these pages: https://www.altera.com/support/support-resources/download/legacy/jrunner.html (https://www.altera.com/support/support-resources/download/legacy/jrunner.html) https://www.altera.com/support/support-resources/download/programming/jam.html (https://www.altera.com/support/support-resources/download/programming/jam.html) https://www.altera.com/en_us/pdfs/literature/an/an414.pdf (https://www.altera.com/en_us/pdfs/literature/an/an414.pdf) http://www.alterawiki.com/wiki/nios_jrunner_example (http://www.alterawiki.com/wiki/nios_jrunner_example)

[Altera_Forum]

Thank you Alex for your suggestion, but MAX10 satisfies us, because it have a wide functionality and low price (MAX10 10M02SCE ~ $7; Cyclone III EP3C5 ~ $16 ). 

And we want to eliminate nesessary of download configuration at production stage.

[Altera_Forum]

Price of the part is one thing to consider, yes. However, at what design cost? Given the lack of documentation are you confident you can even solve this in this way with MAX 10? 

 Given the small size of you device/design, can you not test the design enough to ensure you never need to change it? If you end up having to support remote upgrade in the manner Altera intend for this device (UART/I2C), you're going to increase the complexity of your design enormously and use up a lot of resources. You'll probably end up needing a larger, more expensive, part...  Cheers, Alex

[Altera_Forum]

Thanks all of you for your quick response! 

 I also receive from altera support next recommendations: "Since you mentioned that you would like configure MAX 10 using remote micro CPU, then you may consider to use the Jam Player (JAM STAPL) or JBC Player (Jam STAPL Btye-Code player) to program the .jam file into the MAX 10 device via JTAG. The .jam file is generated from the .sof file, this information can be refer in AN425.To port the Jam Player to the embedded processor, you need to modify the jamstub.c or jbistub.c file (for the ASCII Jam Player or Jam Byte-Code Player, respectively). For details in porting the Jam player, please refer to application note AN425: Using Command-Line Jam STAPL Solution for Device Programming from the following link: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an425.pdf For other relevant information on how to use Jam/JBC STAPL player and porting into embedded processor please refer to the following link:  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an586.pdf You can refer to the following link to obtain the Jam Player (JAM STAPL) or JBC Player (Jam STAPL Btye-Code player): https://www.altera.com/support/support-resources/download/programming/jam.html The Jam/JBC STAPL player source code is an open source, since user can modify the source code into embedded system this is consider as design customization. Please bear in mind that we do not provide any support in design customization on the source code. "  It is close to msj advice.  But we found that Cyclone 4 smallest (~ $6.5) is a bit cheaper then smallest MAX 10 ( ~ $7) and as we don't need to use configuration flash, we decided to use Cyclone 4 with Passive Serial mode for our issue as Ajex adviced.