Configuring Arria V Transceiver PLL for 2.5G Ethernet

[host]

Hello,

I want to use the Multi-rate Ethernet IP at 2.5G on an Arria V device

The datasheet mentions that rx_clkout will be derived from tx_serial_clk:

And it seems like I’ll need to use a Transceiver PLL that operates at 1562.5 MHz.

How do I need to configure the Arria V Transceiver PLL to make it output a clock at 1562.5 MHz?

What PLL base data rate should be used ?

[paveetirrasrie_Intel]

Here's the connection required to operates PLL for 2.5G

Serial clock from transceiver PLLs.

• 2.5GbE: Connect bit [0] to the transceiver PLL. This clock operates at 1562.5 MHz

• 1GbE: Connect bit [1] to the transceiver PLL. This clock operates at 625 MHz.

• 10GbE: Connect bit [2] to the transceiver PLL. This clock operates at 5156.25 MHz. 

Kindly refer to https://www.intel.com/content/www/us/en/docs/programmable/683171/current/clock-and-reset-signals.html for more detailed explanation.

Regards,

Pavee

[host]

Thanks for the input.

I'm using only 2.5G so I need only one clock.

This is my Transceiver PLL component as generated by the IP wizard:

I have doubts about how to connect the following singals:

1. pll_fbclk (input)

2. fboutclk (output)

3. hclk (output)

[paveetirrasrie_Intel]

Hello,

Quartus will help on configuring PLL automatically.

Complete the following steps to configure a Transceiver PLL IP Core:

1. Under Tools > IP Catalog, select the device family of your choice.

2. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY> Transceiver PLL .

3. Specify the options required for the PLL.

4. Click Finish to generate your parameterize Transceiver PLL IP Core.

Regards,

Pavee

[host]

That's exactly what I did:

And the PLL is generated as follows:

How should I connect the following ports ?

1. pll_fbclk (input)

2. fboutclk (output)

3. hclk (output)

[paveetirrasrie_Intel · Accepted solution]

Hello,

After checking on this, here's the connection guideline:

•  The proper connections are to connect "fboutclk" to "pll_fbclk" and to leave "hclk" open.

Hope I've answered your query.

Regard,

Pavee

[paveetirrasrie_Intel]

Hello,

I’m glad that your question has been addressed, I now transition this thread to community support. 

If you have a new question, feel free to open a new thread to get the support from Altera experts.

Otherwise, the community users will continue to help you on this thread. 

Thank you.

Regards,

Pavee