Configuring Arria V Transceiver PLL for 2.5G Ethernet

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Configuring Arria V Transceiver PLL for 2.5G Ethernet

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Hello,

I want to use the Multi-rate Ethernet IP at 2.5G on an Arria V device

The datasheet mentions that rx_clkout will be derived from tx_serial_clk:

And it seems like I’ll need to use a Transceiver PLL that operates at 1562.5 MHz.

How do I need to configure the Arria V Transceiver PLL to make it output a clock at 1562.5 MHz?

What PLL base data rate should be used ?

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Configuring Arria V Transceiver PLL for 2.5G Ethernet

PLL|Clock Management