Configuring Arria10 from HPS

[Fox0197]

Hello everyone,

I'm using the HAN Pilot Platform with the Arria 10AS066K3F40E2SG FPGA Chip.
Quartus Version 24.3
Embedded Shell Version 20.1

I want to configure the FPGA via HPS on a very basic level, like this https://github.com/zangman/de10-nano/blob/master/docs/Flash-FPGA-from-HPS-running-Linux.md .

Therefore i compiled the GHRD Project for the Platform and generated a bootloader and kernel accordingly to this guide from rocketboards (https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10).
U-boot branch: socfpga_v2024.04
Kernel branch: socfpga-6.6.22-lts

The rootfs is a debian bookworm which i generated by following information from this link (https://github.com/zangman/de10-nano/blob/master/docs/Debian-Root-File-System.md).
The bootlader, kernel and OS are working fine (at least from my perspective). No errors are shown in the logs during boot and basic operation of the OS.
Now if I want to configure the FGPA from the HPS I follow the information provided at the top of the post.

In my generated dtb (which I generated at the kernel generation step) a soc/base_fpga_region placeholder exists. And I generated a dtbo file to load the overlay.
The command (echo -n "blink.dtbo" > blink/path) for loading the device tree overlay fails in the shell with the following error message: "-bash echo: write error: Invalid argument"

If I look into the fpga_manager status i get: "write init error"

If i look at dmesg and get:
"fpga_manager fpga0: writing blink.rbf to SoCFPGA Arria10 FPGA Manager"
"fpga_manager fpga0: Error preparing FPGA for writing"
"fpga_region region0: failed to load fpga image"
"OF: overlay: overlay changeset per-apply notifier error -22, target /soc/base_fpga_region"

So far I checked everything for errors in compilation and logs. I also searched for other guides and ressources but could not find anything specific.

Unfortunately i cant find my errors, could you please help me solving this issue?

Thank you in advance for all replies

[Jeet14 · Accepted solution]

Hi,

I found the below link where it is mentioned that configuring the FPGA fabric from Linux using the Linux device tree overlays method is not supported in Intel® Arria® 10 SoC FPGA

https://www.intel.com/content/www/us/en/support/programmable/articles/000090173.html

But, you can use the partial reconfiguration (PR) solution where Linux device tree overlays method is supported.

https://www.rocketboards.org/foswiki/Projects/Arria10SoC170HardwareReferenceDesignThatDemostratesPartialReconfiguration

Regards

Tiwari

[Fox0197]

Hi Tiwari,

thank you very much for your response.

I tried the partial reconfiguration solution you mentioned.

I kept my current Quartus and kernel versions and followed the guide from RocketBoards. Since I am using a more recent version of Quartus, some steps—such as selecting the synthesis mode for a revision—are no longer available in the Revisions window. Additionally, the Freeze Controller Intel FPGA IP is no longer listed in the IP Catalog, as it has been deprecated? Instead, I used the Partial Reconfiguration Controller Intel FPGA IP which contains the freeze controller. Based on the information from Intel's AN797 guide (https://cdrdv2-public.intel.com/666943/an797-683497-666943.pdf), I managed to create a design (base implementation and persona implementation) that compiled successfully without errors.

Unfortunately, the resources from the RocketBoards website—such as “linux-socfpga-pr-17.0-a10.tar.gz”—are no longer accessible, so I couldn’t check the DTBO files. I assume the RocketBoards guide is based on Intel’s AN798 guide (https://cdrdv2-public.intel.com/667007/an798-683034-667007.pdf), so I used the DTSO files provided there.

Unfortunately, I encountered the same error when trying to apply the device tree overlays for partial reconfiguration.

I am trying to use modern software versions because I want to maintain an up-to-date system for the partial reconfiguration approach.

Over the weekend, I will attempt to build a design using the older Quartus version and the previous kernel in order to get a working design.
I will update you on Monday.

Best regards,
Fox

[Fox0197]

Hello,

I managed to solve the problem today.

It is necessary to make an adjustment in the DTS file of the linux kernel "socfpga_arria10.dtsi".
You need to set #address-cells to 0x2, otherwise programming the FPGA will not work.

Many thanks for the quick help.

Best regards,
Fox

[Jeet14]

Hi,

Thanks for the update.

Now, I will close this case.

[Jeet14]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.