Configuring Cyclone V with SVF/JTAG

[LUT]

I have a design that uses urjtag/FTDI2232 to configure a Cyclone V via JTAG using an SVF file. The FPGA seems to get configured reliably, but the lone verification command in the SVF always fails.

So

SIR 10 TDI (002);
SDR 56167760 TDI (....);

succeeds but

SIR 10 TDI (004);
SDR 1488 TDI (...) TDO (...) MASK (...)

always fails.

The original svf file was generated with Quartus 12.1. I have also tried converting the .sof to .svf with 18.1, both GUI and command line, without any change in behavior. Changing the TCK clock rate had no effect.

I assume IR (002) is configure and IR (004) is some kind of verify step? But the concern is that the IR (004) instruction is doing more than just verifying the configuration.

Is anyone else out there using an FTDI 2232 to configure via JTAG? Did you need to modify the quartus generated SVF? Are you using urjtag or something else to interface to the 2232?

Thanks for any help/pointers/suggestions.

[YuanLi_S_Intel]

Hi Sir,

Apologize that programming Altera FPGA is not our main programming method. We use Quartus Programmer to program FPGA.

I found some guide from FTDI chip, hopefully it helps:

https://www.ftdichip.com/Support/Documents/AppNotes/AN_377%20Altera%20FPGA%20FIFO%20master%20Programming%20Guide.pdf

Thank You.

Regards,

Bruce