Configuring a NIOS II / SDRAM from the HPS

Altera_Forum · ‎06-17-2014

My system design requires the HPS as well as one or perhaps two NIOS II processors. At the moment I am just trying to get one NIOS II processor running.

My aim for field firmware upgrades is to be able to copy a file to the HPS SD Card via SCP (drag and drop in WinSCP).

On reboot the HPS will find the most recent FPGA image and use that to configure the FPGA. All fine so far.

My question is:-

How can I extend this scheme such that I can initialize the SDRAM, so that the NIOS processor can be started?

Thanks

Altera_Forum · ‎06-18-2014

Your NIOS runs in HPS SDRAM, not in onchip memory ?

If HPS program is too big and runs in SDRAM, may be intersection of read/write regions both processors and slow execution.

For NIOS is better using 2nd copy of SDRAM, connected to FPGA.

If HPS see memory, where NIOS is running, it may fill there NIOS region with previously saved contents from file on SD, when NIOS work. After configuring FPGA NIOS starts from reset address and see his code is ready in SDRAM. This snapshot of working NIOS-memory will be getted also from NIOS with "semihosted" file in debugger:

int main() {
# ifdef _SAVE_CODE_TO_HOST_ && 1 // conditional include/exclude
  static bool first_run = true;
  if (first_run) {
    first_run = false;
    FILE *f = fopen("my_NIOS_sd_cod.bin", "wb");
    fwrite((void*)SDR_NIOS_ADDR, SDR_NIOS_SIZE, 1, f);
    fclose(f);
  }
# endif
  // ...ordinary working...
}

In "live" start variable first_run will be false, and saving NIOS code to host omitted.

This file "my_NIOS_sd_cod.bin" will be located on SD card together with .rbf file.

Altera_Forum · ‎06-20-2014

Thanks for the reply.

My system architecture is HPS with 1GB DDR3. FPGA/NIOS II with 64MB SDRAM. It's actually a Terasic DE1-SoC but the production board will use the same components for easy migration.

Do you have any more comments based on this information?

Altera_Forum · ‎06-20-2014

Is too big memory sizes for embedded tasks! Your programs on HPS&Nios may use more than 1(10)M of memory?

What is task of Nios ? May he fit to 64K of onchip FPGA-RAM and boot from .hex-file in Quartus project ? My tasks tamps to onchip!

HPS have access to Nios-SDRAM № 2? Then hi also may read Nios-SDRAM-memory and save to SD-file, when Nios stopped in debugger.