Confused about the BRAM read result

[Altera_Forum]

Hi,all 

 I can write data into BRAM correctly, but for read process I feel rather confused about what's going on. In read process, it read data out when condition met, then send it over the RS232 line. I found that the sequence it sends isn't my expectation when all data load is the same. Even more, when I load different data into the RAM, it sends unorderly data. Any reply welcome!   Here are part of program, data_ram3 is 2-d array which is synthesized as BRAM. when sd_ram1=>  if loop_ct2/=501 then  second_state<=sd_ram1;  if trans_done_rising='1' then  if pingpang=0 then data_send<=data_ram3(loop_ct2)(12 downto 8); pingpang<=pingpang+1;----need to check the syntax. elsif pingpang=1 then data_send<=data_ram3(loop_ct2)(7 downto 3); pingpang<=pingpang+1; else data_send<="00" & data_ram3(loop_ct2)(2 downto 0);loop_ct2<=loop_ct2+1;pingpang<=0; end if;

[Altera_Forum]

Hi,all 

  Does anybody fimiliar with the Block RAM enbedded in Altera device read process,especially for VHDL description which can be synthesized into BRAM&#65311;

[Altera_Forum]

have you followed the altera coding guidlines in the quartus manual, section 10? 

 http://www.altera.com/literature/hb/qts/qts_qii51007.pdf