My board has Stratix II , EPCS64 device and RS422 UART on it, RS422 UART is used for comunication with PC. I try to build design that will remotely update and trigger the reconfiguration of Stratix II, the configuration is stored in EPCS64.
At this point I want to avoid using NIOS for remote configuration,
so the simple design I had in my mind was to build custom logic that will look something like that:
*) EPCS64 will accommodate the factory image and the user configuration image.
*) The PC will send the new user configuration image over UART RS422, custom logic will write the image to EPCS at the right address.
*) The custom logic will be comprised of interface to PC, interface to EPCS and simple control logic to control transaction to EPCS.
*) The reconfiguration process will be done using ALTREMOTE_UPDATE megafunction.
But now I am confused :confused: with the following essue:
ALTREMOTE_UPDATE generates "pgm" signal to select the image for the configuration. EPCS do not have those "pgm" pins, so I have to build logic that decode\translates "pgm" signal to sector address on EPCS, However it seems as "pgm" signals genereted by ALTREMOTE_UPDATE are not accessable to the logic inside the FPGA, so is there no way to decode "pgm" without external logic?
Thank you.
