Constraining a high speed design

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Hello, 

I am trying to constrain ASI soft receiver on Cyclone III EP3C40F324. There are two instantiations of the ASI megacore, but I rarely get both of them to work correctly, most of the times, I get lost packets.  I am fallowing ASI user guide appendix A, available here: http://www.altera.com/literature/ug/ug_asi.pdf  According to page A-5, I set my design constrains: # Oscillator inputs: 27MHz create_clock -name clk_in -period 37.037 create_clock -name clk_in2 -period 37.037 # PLL commands derive_pll_clocks derive_clock_uncertainty # ASI# Set false path for input pins, since these signals already carry a clock (HM, NOT SURE?)# set_false_path -from }]# set_false_path -from }] set_min_delay 0.00 -from {PLL1|altpll_component|auto_generated|pll1|clk} -to {PLL1|altpll_component|auto_generated|pll1|clk} set_max_delay 4.43 -from {PLL1|altpll_component|auto_generated|pll1|clk} -to {PLL1|altpll_component|auto_generated|pll1|clk}   I am not sure if setting ASI serial inputs as false paths is correct? PLL1 generates required oversampling and clocks: c0 - 337.5MHz 0deg c1 - 337.5MHz 90deg c2 - 135MHz  According to page A-3, I set specific register locations to required LABs:  set_location_assignment LAB_X32_Y2_N0 -to "asirx:ASI2|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_a" set_location_assignment LAB_X33_Y2_N0 -to "asirx:ASI2|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_b" set_location_assignment LAB_X32_Y2_N0 -to "asirx:ASI2|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_c" set_location_assignment LAB_X33_Y2_N0 -to "asirx:ASI2|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_d" set_location_assignment LAB_X22_Y2_N0 -to "asirx:ASI1|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_a" set_location_assignment LAB_X23_Y2_N0 -to "asirx:ASI1|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_b" set_location_assignment LAB_X22_Y2_N0 -to "asirx:ASI1|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_c" set_location_assignment LAB_X23_Y2_N0 -to "asirx:ASI1|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx|serdes_s2p:u_s2p|sample_d"  Result in floorplan: http://i.imgur.com/pc2ik.png  I don't see any timing problems in TimeQuest regarding ASI, but I am not sure if I've constrained it correctly. If I don't set asi_rx [*] pins as false path, then I am not sure how do I constrain these inputs. I do have other problems with timing (related to system and another clock), but maybe later about that.  Thank You.