PCIe Switch implementation on FPGA

[Altera_Forum]

Hi, 

I want to implement a PCIe Switch with one Upstream and with four Downstream port one lane each. My question is can I locate all four diffrential pairs pins in one IO-Bank using one clock. Thanks In advance :) Elad

[Altera_Forum]

There's no way anyone can answer this question. You have not mentioned the FPGA device you are planning to use. 

 Please use Quartus to answer this question; instantiate the PCIe cores and synthesize the design. If Quartus lets you do it, then you can :)  Note that you don't have to put logic on the fabric side of the interface, just drive signals to valid logic levels. When I've done this with ALTGX components, they are preserved (even though the logic does nothing).   Cheers, Dave

[Altera_Forum]

Thanks for your replay!! 

I tried but it wan't work. I am using Startix IV for this implementation.  I am using 4 ALTGX working at PCIe protocol.    Worth mentioning that when I am connecting the 4 diffrential pairs to diffrent banks every thing works fine  Elad

[Altera_Forum]

--- Quote Start ---   I tried but it wan't work.    --- Quote End ---   Tried what exactly? 5 instances of a x1 PCIe core? How many hard-IP PCIe cores does your device have?    --- Quote Start ---   I am using Startix IV for this implementation.  I am using 4 ALTGX working at PCIe protocol.     --- Quote End ---     Which device? Does it have 4 PCIe hard-IPs?  Why do you want to implement a PCIe switch in an FPGA, when PLX and IDT sell these types of devices at a fraction of the cost of an FPGA?  You might want to re-think your architecture, and just use the FPGA where you need customization.  Cheers, Dave