Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
750 Views

Constraining byte deserializer after ALTLVDS_RX

Hello everyone. 

I just ended up with problem using ALTLVDS_RX megafunction. 

I need to recieve 12 bit data from CMOS sensor (ADC is not adjustable for 10 bit resolution), so I generated 6 bit ALTLVDS_RX with external PLL and a byte deserializer with mod-2 counter. 

Now I have 6 bit input with 74.25 MHz clock and 12 bit output with 37.125 MHz clock generater from the same PLL. 12 bit output register is feeded by 74.25 MHz clock. After that I want to use 37.125 MHz as main system clock for image processing. Everything compiles but TimeQuest told me that nothing will work. My SDC file contains: 

-create_clock.... 

-derive_pll_clocks -create_base_clocks 

-derive_clock_uncertainty 

 

So I suppose that I need to tell TQ that CLK_EN on 12 bit register force it to refresh half of the feeding clock, and everything is fine and synchronous, but I don't know how to, except set_fallse_path, but I think it's not the right solution.
Tags (2)
0 Kudos
0 Replies
Reply