Conversion uses all combinational logic

[Altera_Forum]

Hi, 

 I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip.  type DATE_ARRAY is array(5 downto 0) of integer range 0 to 2100;variable SC_Var : std_logic_vector(7 downto 0) := x"00"; variable MN_Var : std_logic_vector(7 downto 0) := x"00"; variable HR_Var : std_logic_vector(7 downto 0) := x"00"; variable DT_Var : std_logic_vector(7 downto 0) := x"00"; variable MO_Var : std_logic_vector(7 downto 0) := x"00"; variable YR_Var : std_logic_vector(7 downto 0) := x"00"; variable DW_Var : std_logic_vector(7 downto 0) := x"00";date := ntpToRTC(timestamp_var); SC_Var := std_logic_vector(to_unsigned(date(0),8)); MN_Var := std_logic_vector(to_unsigned(date(1),8)); HR_Var := std_logic_vector(to_unsigned(date(2),8)) or x"80"; DT_Var := std_logic_vector(to_unsigned(date(3),8)); MO_Var := std_logic_vector(to_unsigned(date(4),8)); YR_Var := std_logic_vector(to_unsigned(date(5),8)); DW_Var := "00000000";  The function I call fills the data with integers representing year, month, day... I also tried putting each conversion in a sepearate state and it made no difference.  Any help much appreciated

[Altera_Forum]

The question isn't understandable. A to_unsigned() conversion doesn't consume logic cells at all.

[Altera_Forum]

This wont be your problem, as FvM says type conversions use no logic (at the end of the day, an integer is still N bits). Do you have some loops in your code? recursive functions? 

 please post the rest of your code.

[Altera_Forum]

I attached the VHDL

[Altera_Forum]

To understand about the problems involved by your design, you can do like this: 

 Compile the design without a particular FPGA selected. e.g. Cyclone III, auto device selection. Then browse the Resource Utilization by Entity category in Compilation report/Analysis and synthesis.  You'll notice, that most of the 18k LEs is consumed by the various large dividers in your design (including mod operations, which also uses dividers). Parallel dividers have a huge resource utilzation and should be avoided, if possible.  This is a kind of design that's not well suited for FPGA implementation. There are surely options to reduce the resource usage. Implementing slow serial dividers would be an obvious one.

[Altera_Forum]

Looks like you're trying translate a C file - you even called your file main.vhd.  

 Id say go back to the drawing board. Think about what logic you're trying to implement and draw it out by hand before even touching a keyboard to type in any VHDL code.

[Altera_Forum]

--- Quote Start ---  You'll notice, that most of the 18k LEs is consumed by the various large dividers in your design (including mod operations, which also uses dividers). Parallel dividers have a huge resource utilzation and should be avoided, if possible.  --- Quote End ---  I'm sorry but what is an 'LE'? When your talking about the divide and mod operations, I assume your referring to the functions? If I implemented all those operations each in its own state is that what you mean by serial division?    --- Quote Start ---  Looks like you're trying translate a C file - you even called your file main.vhd.   --- Quote End ---  Actually your mostly correct. The part I tried to translate from C was the functions, the rest I wrote with VHDL in mind.  How could I implement the algorithms without utilizing so many resources?  Thank you to everyone, your very helpful

[Altera_Forum]

A "LE" is a logic element. Different devices have different numbers of them.  

 Basically, this is going to need a complete re-design. You will have to cope with limited numbers of dividers, maybe 2 or 3 , rather than the 20 or so you have in your design. Each divider should also have a latency of several clock cycles, rather than the asynchronous versions that are implemented in your code (interestingly, Timequest crashes while trying to assess your design!). The current code has many unclocked dividers between registers that will limit your max clock speed to something very slow.  My Recommendation would be to start from scratch. Think about the design logic and draw it all out before you write any VHDL.

[Altera_Forum]

As a quick note to your very very slow design - I compiled it for a stratix 4 - and timequest said the max clock speed for your design would be 1.5MHz. On a Cyclone 2 it would be much slower. 

 So you need to sort out your design with decent pipelining.

[Altera_Forum]

--- Quote Start ---  The current code has many unclocked dividers between registers that will limit your max clock speed to something very slow.  --- Quote End ---   That's true, but considering the design purpose, it could run at kHz clock speed without problems. The basic problem is the large amount of wide dividers. But if the design is intended to learn HDL programming, then pipelined dividers shoul be used.  An addional problem is created by using unrestricted integer type for most signals. The design compilers isn't able to recognize the actual needed number ranges.   Generally, the design style suggests a lack of understanding how hardware logic works. It would be interesting challenge to find an FPGA adequate coding of the present problem. But I wonder, if it's more reasonable to start with a more simple arithemetic problems.

[Altera_Forum]

This is part of a network time protocol server. The main.vhd is a bridge between a GPS interface which converts and parses time from the GPS to an NTP timestamp. It converts that time and periodically writes it to a real time clock. The design works perfectly until the addition of the functions getjulianday(), rtctontp(), and ntptortc(). The problem is I need to essentially convert a 32 bit vector representing seconds since 1901 to date and time, and back again. When I remove the functions and leave the states for converting RTC to NTP timestamp and vice versa blank, it compiles fine and functions correctly. I understand what you both mean by the problem with the dividers. But I'm unsure about the clock speed. My clock is 24.76Mhz and it works fine (without the functions for converting) on the board. How can I implement the algorithms without encountering the same problems?

[Altera_Forum]

Its the functions that add all of the dividers, that kill your FMAx down to 1.5MHz, because none of them are clocked (you are calculating all those values in a single clock cycle, so there are no registers between the input and output of the function). 

 One answer would be to break up the functions and pipeline them. You could then feed in the Timestamp to calculate minutes, then repeat after this completes to calculate minutes and so on. Store the results in registers, and when they're all complete send a ready signal back.

[Altera_Forum]

Someone mentioned that the integer variables I'm using dont have a specified range. So the max size I want them to be is 32 bits long. I set the range to be 0 to 4294967295 (2^32 -1) and I got an error 

   --- Quote Start ---  Error (10528): VHDL error at Main.vhd(196): value "0" is outside the target constraint range (0 to -1)  --- Quote End ---    Which makes sense because a value of xFFFFFFFF in a 32 reg signed would be -1. So I removed the initialization of the integers to 0 and everything compiled fine. Like someone mentioned the division was unknown width so the compiler was having trouble. Regardless its compiling fine now. Thanks to everyone!

[Altera_Forum]

I think you may be misunderstand VHDL. 

 Integers in VHDL are of the range -2^(31) to 2^31 - 1. So the numbers are always signed. You cannot have a range of 0 to 2^32-1 in VHDL. YOu have to use unsigned/signed types for numbers with larger ranges.

[Altera_Forum]

I declared them as type natural and I still get the same problem... 

 variable timestamp_int : natural range 0 to 4294967295 := 0;    --- Quote Start ---  Error (10528): VHDL error at Main.vhd(133): value "0" is outside the target constraint range (0 to -1)  --- Quote End ---  

[Altera_Forum]

natural is technically only 31 bits, because it is a subtype of integer. It has a range of 0 to 2^31 -1.

[Altera_Forum]

What type can I use for a 32 bit unsigned value so that it would have a range from 0 to 2^32 - 1?

[Altera_Forum]

the unsigned type from the numeric_std library 

 variable n : unsigned(31 downto 0);

[Altera_Forum]

I cant seem to use the unsinged type the way I would a natural or integer, it wont let me assign a value to it  

 variable n : unsigned(31 downto 0) := 0;

[Altera_Forum]

To assign a constant value to an unsigned variable/signal, you have to use a constant with a length specification, a conversion function (e.g. conv_unsigned) or an expression like n:=(others => '0');

[Altera_Forum]

I'm trying to pipeline the algorithm. I seperated the function so that there are very few operations in each stage. I essentially broke each function into a state machine where an operation is performed on each state. This still is too much for the synthesis and I dont know why? Shouldn't it only be using a single adder or multiplier in each state?