Converting Behavioral to Gate Level

[Altera_Forum]

I want to convert my behavioral VHDL description to its gate level one. How can I do this using Quartus II? 

 Regards http://www.alteraforum.com/forum//proweb/misc/progress.gif

[Altera_Forum]

If you are using the Quartus native simulator, just run a timing simulation instead of a functional simulation. 

 If you are using a third-party simulator, you can start with Quartus on-line help.  On the help Contents tab, go to "Integrating Other EDA Tools --> Specifying EDA Tool Settings". This page tells you how to generate the .vho or .vo gate-level netlist with Quartus.  On the help Contents tab, go to "Integrating Other EDA Tools --> Using Other EDA Simulation Tools --> About Using the <third-party> Software with the Quartus II Software --> Performing a Timing Simulation with the <third party> Software".

[Altera_Forum]

I want to convert my RTL verilog description to gate-level or something like that. Some say that this can be done using the .vo file generated by Quartus. But I opened it and found nothing. It was just some instantiations from alteras components. Is there a way to do that?

[Altera_Forum]

--- Quote Start ---  But I opened it and found nothing. It was just some instantiations from alteras components.  --- Quote End ---   It is a true gate level represantation of your design. What do you expect in this place?

[Altera_Forum]

I don't know! In fact I can't find out what it is? I want pure gate level transaltion of my behavioral code. Can I get it from Quartus?

[Altera_Forum]

If you mean a description using e.g. AND, OR, FFs? *.vo/*.vho are using the gate level, that is actually present in FPGA, these are LEs consisting of a LUT and a FF. The LUT logic uses basic logic equations, and thus can be displayed as a gate circuit, if you want to.  

 In the gate level file, it's represented twice, by a binary lut_mask, specific to the involved FPGA family and a comment with a readable logic equation. But it's AHDL (ABEL) syntax rather than Verilog or VHDL.   It's not producing a pretty printed HDL gate level file.

[Altera_Forum]

I want just some lower level of description without always block and something like that. I need a description which let me to convert it to pretty gate level using a C program. Can it be done?

[Altera_Forum]

As I said, the equations in the comment lines are readable and can be converted to other HDL language. If I remember right, the syntax is described in Quartus online help or a software manual. But it's using basically only four operators ! &# $ (NOT, AND,OR,XOR), so the meaning should be understandable without further documentation. Cause the gate level file has to reproduce the exact LUT implementation of the design (to allow correct timing analysis), it may differ considerably from the virtual gate level representation, you're intending.

[Altera_Forum]

TO_BE_DONE