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Valued Contributor III
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Create own Avalon MM-Slave

Hi there 

 

I'm trying to create my first Avalon MM-Slave which should be accessible through a NIOS II softcore. In the end I just want a MM-Slave which has a conduit input and output for connecting to my custom logic. I am using a very simple MM-Slave which I have found on the internet to test how the slave behaves and how I have to build up my own slave with my needs. The slave works so far and I'm basically able to read from and wirte to the slave. But there is something I do not understand: 

 

The component uses the following entity: 

entity system_cpu_serial_interface_2 is port( -- Avalon Clock interface clk : in std_logic; -- Avalon Reset interface reset : in std_logic; -- Avalon-MM Slave interface address : in std_logic_vector(1 downto 0); read : in std_logic; write : in std_logic; readdata : out std_logic_vector(31 downto 0); writedata : in std_logic_vector(31 downto 0) ); end system_cpu_serial_interface_2; 

 

When reading from the slave I use the following line in my NIOS II code: 

result = IORD_32DIRECT(SYSTEM_CPU_SERIAL_INTERFACE_2_0_BASE, 1); 

 

I was expecting that I see the chosen offset (which is in this case 1) on the address signal. But what I get is the following:https://alteraforum.com/forum/attachment.php?attachmentid=15023&stc=1  

writedata changes to 0x00000001 during read and address stays 0x00 (see attachment read.jpg).https://alteraforum.com/forum/attachment.php?attachmentid=15028&stc=1  

 

When I try to write to the slave, the behaviour is different. I use the following code in NIOS II: 

IOWR_32DIRECT(SYSTEM_CPU_SERIAL_INTERFACE_2_0_BASE, 2, 0xAAAAAAAA); 

 

In signal tap I can see that writedata now is 0xAAAAAAAA as expected but again, the address signal stays 0x00. I was expecting this time that address should be 0x02 since the offset was 2 (see attachment write.jpg). 

 

Can anyone tell me why the component behaves like this and how can I reach that i see the offset when reading or writing on the address signal? 

https://alteraforum.com/forum/attachment.php?attachmentid=15029&stc=1
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Valued Contributor III
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Hi, 

 

Can you attach the RAM read-write logic used? 

it may be because of that logic issue.Follow the timing diagram from below attachment 

https://www.altera.com/en_us/pdfs/literature/ug/ug_ram_rom.pdf 

 

Let me know if you need any further assistance. 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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I doubt it would make a difference, but what happens if you use just IORD and IOWR instead of the 32DIRECT commands you used? 

 

Also, in Qsys (Platform Designer), what have you set as the base address of this component? And since you're using Signal Tap, what does the address look like on the master side instead of the slave side? Maybe there is some weird address translation or something going on here.
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Valued Contributor III
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--- Quote Start ---  

Can you attach the RAM read-write logic used? 

--- Quote End ---  

 

Anand Raj, I'm not sure what RAM read-write logic you mean. Are you talking about the on-chip memory of the NIOS II? If yes, there was no explicit read-write logic generated by Qsys (see attached porject_overview_1.jpg). Or are you talking about the template I found on the internet (if yes then look at the attached file system_cpu_serial_interface_2.vhd)? Or does the avalon interconnect have a RAM for read- and write data (there are a lot of components generated for the interconne? 

 

 

--- Quote Start ---  

it may be because of that logic issue.Follow the timing diagram from below attachment 

https://www.altera.com/en_us/pdfs/li...ug_ram_rom.pdf 

--- Quote End ---  

 

I don't see the connection between my problem and the document you attached. Do you wanna say that I have a problem with a RAM or do you mean that there is a general timing issue with the Avalon bus? 

 

 

--- Quote Start ---  

(...) what have you set as the base address of this component? 

--- Quote End ---  

 

The base address of the component is 0x0008_1040 

 

 

--- Quote Start ---  

And since you're using Signal Tap, what does the address look like on the master side instead of the slave side? 

--- Quote End ---  

 

This was also my intention and I did also capture a shot where the master signals are included (see attachment st_master_signals.jpg). But for me it is pretty hard to debug on the master side, since I don't know the master in detail. 

 

 

--- Quote Start ---  

I doubt it would make a difference, but what happens if you use just IORD and IOWR instead of the 32DIRECT commands you used? 

--- Quote End ---  

 

This is it! It makes a difference! If I use the IORD and IOWR it works as expected. But whats the difference between IOWR and IOWR32DIRECT?
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Valued Contributor III
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I did some testing today and modified the component to my needs. It seems that the bus now works with IORD and IOWR. But I'm still struggling with the address signal. When writing to the component the address signal is still not right. I used the following line in NIOS II software to write dummy data to the component: 

 

IOWR(SYSTEM_CPU_SERIAL_INTERFACE_2_0_BASE, 1, 0xbeef); 

 

The offset I use is 1 but the address signal swaps between 2 and 3 (see attached component_wirte.jpg). The same happens when reading from the component (see attached component_read.jpg, used an offset of 5), the address signal is not correct and swaps.
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Valued Contributor III
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Assuming you created this as a custom component using the Component Editor, what are your settings on the Signals & Interfaces tab in the Component Editor for this slave interface? You may have set something that is affecting the address translation through the interconnect.

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Valued Contributor III
21 Views

 

--- Quote Start ---  

Assuming you created this as a custom component using the Component Editor, what are your settings on the Signals & Interfaces tab in the Component Editor for this slave interface? 

--- Quote End ---  

 

 

Yes, I did create the custom component in Qsys. You can see the signals setup in the attached component_setup.jpg picture. I did also attach the components .vhd file. Maybe I also did something wrong with the component itself!?
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Valued Contributor III
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What is the data width of the master? If it's 32 and this component is 16, this is where the issue may lie.

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Valued Contributor III
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--- Quote Start ---  

What is the data width of the master? If it's 32 and this component is 16, this is where the issue may lie. 

--- Quote End ---  

 

 

I had some time now to modify the slave for 32-bit read and write data. Now it works. Address is now correct and I'm able to read and wirte to the slave. Thank you very much for the hint!
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