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Hi
I got the following critical warning when I tried to compile my code. Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. Clock Hold: 'pll_80_to_64:Inst_PLL|altpll:altpll_component|pll_80_to_64_altpll:auto_generated|wire_pll1_clk[0]' Is it compulsory to get rid of this critical warning? If so, what should I do to get rid of it?Link Copied
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--- Quote Start --- Hi I got the following critical warning when I tried to compile my code. Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. Clock Hold: 'pll_80_to_64:Inst_PLL|altpll:altpll_component|pll_80_to_64_altpll:auto_generated|wire_pll1_clk[0]' Is it compulsory to get rid of this critical warning? If so, what should I do to get rid of it? --- Quote End --- Hi, can explain the problem more detailed (.e.g. list a path ...) Kind regards GPK

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