Custom Component Address Mapping

[Altera_Forum]

I have a custom component with a 8 bit ADDRESS bus. it is mapped in my hdl code this way :  

 ....   if (read & (address==8'h01))  readdata<=2;   ....   In my SOPC builder system it is mapped this way : base:0x00000000 end:0x000000ff I've done several tests and found out that when I perfrom an IORD action, my custom component does't get the right address. Is there any problem with the different size of address buses of Nios and my custom component? Plz help me :(

[Altera_Forum]

Is your data bus 8 bits wide too? 

you must be careful in that case, because the CPU always does a 32 bits access, which will be converted to 4 8 bits accesses. The second parameter in IORD is a register number in a 32-bit registers space, which means that if your data bus is 8 bits wide, a IORD(base_address,0) will read addresses 0,1,2,3 and IORD(base_address,1) will read addresses 4,5,6,7.  It is usually better to make components with 32-bit data buses, it can avoid some trouble.

[Altera_Forum]

yea my data bus is 8 bits wide!! is this problem independent of the size of the variable we assign IORD to ? for example whether we use: 

""unsigned char a=IORD(componenet_base,0x10)"" or ""int a=IORD(component_base,0x10)""   the cpu does 4 read actions? (assuming the cumponent's data bus width is 8) ?  another questions : my compent has an 8 bit address bus. how is my 8 bit address mapped into the 32 bit Nios address bus ? the 32 bit address is truncated to an 8 bit address bus?

[Altera_Forum]

Yes, IORD always performs a 32bit access, even if you assign a char or a alt_u8 variable. 

In case of a 8bit data bus, like yours, you'll always have 4 read accesses. Note that this applies even if you use IORD_8DIRECT: this was reported somewhere in the forum as an Avalon bus anomaly.  Regarding address, the system interconnect fabric generated by sopc builder automatically selects the right slave when your system performs a memory access. Then the slave must decode only addresses within its range. You can refer to SOPC builder user guide for more detailed information.

[Altera_Forum]

with  

--- Quote Start ---  unsigned char a=IORD(componenet_base,0x10)  --- Quote End ---  The CPU will do one 32-bit read access to the component's register 0x10, which the switch fabric will change into 4 8-bit read accesses at registers 0x40,0x41,0x42 and 0x43 (notice the register number shift). It's a lot easier to do a 32-bit data bus, even if you only use the low 8-bits. It will save you a lot of trouble.

[Altera_Forum]

what if we use PIO s of width eight and perform instructions like :  

IORD_ALTERA_AVALON_PIO_DATA ? does it still perfrom 4 read actions? I still don't understand how the 32 bit address is connectd to my 8 bit address? somehow it should be truncated? 

[Altera_Forum]

PIOs are always 32 bits. If you create a 8-bit PIO it will just use the low 8 bits of the register, and the CPU will just perform one read. 

Nios 2 is a 32-bit CPU, and assumes it's data bus is 32 bits wide. When you connect 16 or 8 bit peripherals to it then some non optimal side effects can appear, due to the way the CPU accesses the data bus.