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Valued Contributor III

Custom instruction to reduce interrupt latency

I've attached a tar file that contains a Nios II custom instruction that accelerates your interrupt response time. This works with Nios II 5.0 and later. There is already support in Altera HAL and MicroC/OS-II to use this custom instruction. 


Just untar the contents of attached tar file in your Quartus project directory or add it to your Nios II kit components directory (defaults to c:/altera/kits/nios2/components on Windows). Then start up SOPC Builder and you'll see a new custom instruction called something like "Exception Vector" under the custom instruction tab of the Nios II wizard. Just add this custom instruction and re-generate your SOPC Builder system, re-compile in Quartus to make a new SOF, and re-build your HAL or MicroC/OS-II application. You should now have lower interrupt latency. If you really want the lowest latency, use tightly-coupled memories in addition to this custom instruction so that your exception handler code and ISR run without cache misses. 


The custom instruction works by generating the offset of the highest priority interrupt. This replaces a bunch of assembly instructions in the HAL exception handler code that call your ISR. The custom instruction uses a multiplexor with one input for each interrupt connected to your Nios II. If you have many interrupts, you might notice a degradation in your system Fmax due to the mux with many inputs. 


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