I'm using an 10AX115N2F4 FPGA with CvP. We have a flash section at the start containing the factory image which can be used to write the flash, plus the section containing the periphery image for CvP.
Currently we see that when a core image from another build (regarding the periphery part in the flash) is loaded, the FPGA is disfunctional and often the host system crashes. It seems there is no verification in place that checks whether the "pair" of periphery and core match at all.
We are therefore looking for a reliable way to update the firmware in the flash.
This raises the following questions:
- How can we avoid a "wrong" core image being loaded, without knowing the current periphery image that is present in the flash? Think of a customer system where you have no information which version it is currently running
- More important, how can we reliably force the FPGA into booting the factory image *without* using JTAG and without a working core image? Note the periphery is still good, which obviously prevents the 3x-default fallback.
- Is there a way to include a flash-writer into the periphery part, so we can update the flash content without a loaded core image?
Any suggestions are welcome.
We cannot know whether if the core image is correct for the peripheral image. But however, you can check the CVP status register (Page 24) for any core logic configuration error.
The current driver flow provided in Arria 10 CVP user guide (Page 21), doesn't have the default factory image. If your application need it, you may create own driver with that.
Arria 10 CVP User Guide: