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Cyclone 10 GX FPGA Configuration Error


We designed a board with the Cyclone 10 GX (10CX105YF780E5G) and we're attempting to configure the FPGA using JTAG as part of the board bring-up process.

While Quartus Programmer reports 100% Success, the design is not reflected (output pins don't change as expected) and the nSTATUS and CONF_DONE pins appear to report an error condition.

In the following image, Yellow is CONF_DONE, Purple is nSTATUS, and Pink is INIT_DONE. The device settings were adjusted to enable the INIT_DONE signal before generating the configuration file.


At the end of configuration, CONF_DONE LED briefly turns off then remains on, and nSTATUS briefly flashes. INIT_DONE goes low throughout the programming process until the end.

According to AN 250 Configuring Cyclone Devices: "If an error occurs during configuration, the Cyclone FPGA asserts the nSTATUS signal low indicating a data frame error, and the CONF_DONE signal will stay low."

Are we correct that this is the error state we observe?

Prior to programming via Quartus and USB-Blaster II, the board is powered on, the supply rails are sequenced in the correct order, and the nSTATUS LED is briefly on then turns off, which we believe indicates successful POR.

Below is the Configuration portion of our board schematic and the simple verilog design which is being programmed.


gpd212_base.v - Just a few constant outputs, no clocks.



module gpd212_base(
	//input wire MCS_REFCLK,
	output wire EN_G4,
	output wire[3:0] DBG_LED,
	output wire[3:0] DBG

assign EN_G4 = 0;
assign DBG_LED = 4'b1010;
assign DBG = 4'b1010;




Do you have any ideas on how we can troubleshoot the configuration process? It is difficult to gain insight into what is actually going wrong.

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2 Replies

We solved the issue -- You can see in the schematic we used LEDs with series 100 ohm resistance to observe the open-drain status outputs nSTATUS and CONF_DONE. We did not realize these pins are also sampled as logic level inputs during configuration, meaning they need to respect the V_IH input high requirement in order for configuration to succeed.


Replacing the LED and 100-ohm resistor with just a 10k pull-up resistor (as recommended in the design guidelines) solved the issue and then configuration occurs normally. Apparently there is enough current flowing through the LED when the open-drain outputs are released high, that the pin still reads as a logic low, interfering with the configuration process.

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Hi KeeganJ,

I apologize for missing your post. Thank you for the update. We're pleased to learn that the configuration issue has been resolved by substituting the LED and 100-ohm resistor with a 10k pull-up resistor in line with the design guidelines. Consequently, I'll now shift this discussion to community support. Should you have a new question, please initiate a new thread for assistance from Intel experts. Alternatively, the community users will be available to assist you on this existing thread. Thank you.



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