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Cyclone 10 GX IBIS models

fkeflkafakawfkawlfja
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I'm trying to use some of the IBIS models for the Cyclone 10 GX. I want to use the models with the internal 50 Ohm Thevenin termination for the OCT (on chip termination). Specifically, the "18_rtio_r50_hv" model, which is the 1.8 V LVCMOS with 50 Ohm termination without calibration.

 

When I use the model in Cadece SigXplorer to simulate the signal integrity, the reflections I get suggest no internal terminations.

 

Is there a problem with the models? Am I expected to manually add the resistors external to the model?

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AqidAyman_Intel
Employee
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Hi,


Please refer to the attached screenshot, where I got from the visual IBIS software. It shows that in the model there is 50-ohm terminations, I believe.


Regards,

Aqid


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Mengzhe
Employee
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Hi,


ibis models have been tested the correctness, so you can follow it.

May I ask what's your simulation process and how to judge OCT is not included?


BR,

Mengzhe


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fkeflkafakawfkawlfja
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Hi, thanks for the reply.

 

I used a generic 1.8 V driver that is included in SigXplorer. Then I connected the driver output to a 50 Ohm characteristic impedance stripline that is 6 inches long. Then I created a bidirectional driver/receiver (IO) set to tristate mode so that I could use the 18_rtio_r50_hv model, and connected this to the other end of the stripline.

 

When I drive a square wave at 100 kHz I was getting extremely large overshoot at the receiver, for example around 2.5 V for the 1.8 V signal.

 

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AqidAyman_Intel
Employee
490 Views

Screenshot from HyperLynx Visual IBIS Editor

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AqidAyman_Intel
Employee
491 Views

Hi,


Please refer to the attached screenshot, where I got from the visual IBIS software. It shows that in the model there is 50-ohm terminations, I believe.


Regards,

Aqid


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fkeflkafakawfkawlfja
458 Views

Thanks for checking. I will see if the software vendor can look into it, since it seems the problem is on their end.

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