Cyclone 10 GX LVDS receiver differential pair pins issue

[MinzhiWang]

Hello Guys,

We encounter one strange issue of C10GX device's LVDS receiver pairs. There are total four pairs used as LVDS receiver. The external differential pair standard may be LVDS or CML differential pairs. So AC coupling capacitors are inserted at each pairs lines.

Figure 1: The hardware default configuration

Above figure 1 shows the interconnection default configuration, and VICM=1.2V. The receiver is FPGA's lvds receiver, and the driver may be external LVDS transmitter or external CML transmitter. Which are provided from following 4 Samtec connectors, as figure 2 shows.

Figure 2: Four Samtec connectors are used to interconnect between differential transmitter and receiver

The issue is that port 0 and port 3 can work well, however, port 1 and port 2 can't work well. Port 1 auto self-generates many pulses, even when it was unplugged. Port 2 always give a high level status. How does this happen?

As figure 3 showing, SignalTap II was used to detect these 4 ports signal status. When they are unplugged, only port 2 (CBA_TRIGGER_2) keeps high level. There are many narrow pulses also appear in port 1, even figure 3 doesn't show them. The issue on port 1 and port 2 will affect them to transfer real signals. For port 1, the noise narrow pulse will be merged into useful real pulses. For port 2, as figure 4 indicates, many unwanted noise pulses appear when driver was plugged.

Figure 3: SignalTap II was used to detect four trigger signals

Figure 4: Many noise pulses generated in port 2 when CML/LVDS driver plugged

We did some modification to detect above issue. For instance, we changed figure 1's default configuration to figure 5. The external termination was removed and FPGA on-chip termination was enabled.

Figure 5: Differential interconnection modification. External termination resistors are removed and enable FPGA on-chip 100ohm termination for LVDS receiver

After above modification, port 1 becomes clean now. However, port2's problem still there. Now there are 3 ports that can be used for FPGA to receive LVDS or CML differential pulse signals correctly.

We need more efforts to find why port 2 still has above issue, in the same time, could anybody here help us on this?

BTW, one more test applied on the port 2. The AC coupling configuration was changed to DC coupling, as figure 6. In this case, FPGA LVDS seems to be able to receive CML/LVDS differential pulse signals now, as figure 7.

Figure 6: The port 2 was switched from AC coupling to DC coupling

Figure 7: The port 2 can transfer CML differential pulse signals in DC coupling mode

For LVDS transmitter, DC coupling should be ok. For CML transmitter, its common mode voltage should violate LVDS specifications which are give in Cyclone 10 GX device datasheet. As figure 8 indication, the CML differential signal were measured in AC coupling mode. The left of figure 8 shows the signal before capacitor, the right one shows the signal after AC coupling capacitor. The primary common mode voltage of CML signal is about 2.7V. In DC coupling mode, even after on-chip 100ohm termination, the Vcm still has around 2.3V. Which is beyond the range of LVDS requirement (0~1.85V) given in device datasheet. So why can port 2 work well in this case?

Figure 8: CML differential pulse signal measured at AC coupling capacitor both sides

Thanks

Best Regard

[FvM]

Hi,
I don't know what causes failure of LVDS link in your design, two points are however clear:

- it's normal operation to see spurious signals on open LVDS input as well as continuous H or L level. Differential input buffer has no hysteresis or offset and therefore shows received noise as signal. We even see false valid 10b/8b packets, altough with very low prohability.

- your "differential interconnection modification" is not confirming with Cyclone 10 GX LVDS termination requirements.

If you absolutely need to suppress spurious signals at open input, you may try to add a small DC offset (e.g. 50 - 100 mV) to input bias, although it causes an input asymmetry and decreases SERDES timing margin. You can start with Your figure 5 scheme and add respective pull-up/down resistors.

[MinzhiWang]

Hi FvM,

Yeah, we know that LVDS link may not be stable when LVDS is open. Question is that the issue happened when LVDS link was closed. Then we captured it from closed link to open link. As figure 4 shows, there are total 4 links in our case. We encountered similar issue on link 1 and link 3 at the very beginning. We have resolved them. Now we have the similar issue on link 0. We ignore the issue on link 0 because we can't capture it when we use 100MHz sampling clock for SignalTap II. However, we collected unwanted data from link 0 when source board was plugged to link 1, as figure 9.

figure 9: link 0 can receive unwanted data when it opens

The link 0 was capture clean when SiganlTap II run under 100 MHz, however, the unwanted pulse can be detected when SignalTap II run under 500 MHz. So the unwanted noise pulse width should be around from 2 ns to 4 ns.

As you can see in figure 9, link 2 and link 3 are clean in the same situation. By the same way, we also proved that link 1 is same clean as link 2&3.  We are continuing to investigate this issue, but currently we have no clue. We hope someone here can give us some hints for this.