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Cyclone 10 LP Clock input and data in different banks

Altera_Forum
Honored Contributor II
814 Views

Hi, 

 

I am new to Cyclone 10 LP device and plan to use 10CL016YU484C6G device in my design. I have a question related to clock pin and data pin connection for a source synchronous data bus. 

 

A) In a source synchronous interface, is it required to connect data and clock input signals to the same bank (being grouped together in same bank)? 

In other words, can a clock input be connected to CLK dedicated Input pin present in Bank-1 and data bus [15:0] signals be connected to any different bank (say Bank-2 to 8)? 

 

Note: CLK frequency of the bus is 80MHz for the source synchronous interface. 

 

Regards, 

Shareef
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Altera_Forum
Honored Contributor II
106 Views

That sounds absolutely fine. I don't anticipate any problems with that. Constrain the interface appropriately and you shouldn't have any problems. Worst case (which I really don't envisage) you may need to instantiate a PLL - you may wish to do this anyway - to generate a phase adjusted local clock but I really don't anticipate the need for that. 

 

Cheers, 

Alex
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