I am having problems with a Cyclone 10 LP running a Nios processor that is writing spurious data to its configuration device on power down.
I'm using a 16Mbit SPI configuration device and the EPCQ Controller 2 to control it.
I have seen on an oscilloscope that the Chip select and Data lines to the configuration device start toggling on power down for about 600µs. I've also seen that the clock signal remains active even after the device has configured.
I've compared this with a previous project using a Cyclone III and have seen all of the configuration signals become and stay static after configuration has ended.
Does any one have any ideas what might be going on? Especially why is the clock signal remaining active after configuration?
For your Cyclone III project, do you used EPCQ Controller II IP too?
If possible, can you attach the scope from oscilloscope here?
Have you tried used another IP? Is it you got the same issue?
For the Cyclone III project we use the EPCS controller.
When we scope that the CLK signal stops once configuration stops unlike the EPCQ controller with the Cyclone 10 LP.
May I know which configuration device you are using for Cyclone 10 LP? (i.e EPCQ16, MT25Q256 or etc2)
Are you using your custom board or Intel Cyclone 10 LP Evaluation kit?
I tested my Intel Cyclone 10 LP Evaluation kit with EPCQ controller II IP, I did not get any corrupted byte on my flash and DCLK stop once configuration completed.
Maybe you can try to use Intel FPGA Generic QUAD SPI Controller II IP instead of EPCQ controller II.
(the EPCQ or QSPI controller II are the same in term of how to execute it. EPCQ wrap over hard asmi ip while QSPI wrap over soft asmi ip).