Cyclone 10 LP KIT - Ethernet MAC and RAM byte-level access

[vmetodiev]

Hello,

I am a beginner in the Quartus environment and FPGAs in general, trying to figure out how to get byte-level operations from the IPcores for the Ethernet PHY (XWAY PHY11G) and the onboard RAM of the Cyclone 10 LP kit.

I have tried the Ethernet MAC project

https://www.intel.com/content/www/us/en/design-example/714768/cyclone-10-lp-intel-fpga-triple-speed-ethernet-and-intel-on-board-phy-chip-reference-design.html?

but I did not manage to "interface" the input/output with my custom Verilog code.

The same is with the Hyperbus RAM. There is an example

https://www.intel.com/content/www/us/en/design-example/715001/cyclone-10-lp-s-labs-hyperbus-memory-controller-ip-tutorial-003.html?

but I cannot figure out how to use the RAM independently, without the NIOS-II soft processor.

May someone advise how to "extract" the byte-level operations from the Ethernet MAC and the Hyperbus RAM IPcores, without any additional code and automation scripts?

I need to receive Ethernet frames and store them in the memory. I imagine to have access to all the necessary clock/strobes and implement my logic in Verilog, without any soft-cores and high-level abstractions. 

Thank you in advance!

[ZiYing_Intel]

Hi,

Thanks for submitting the issue.

Please do let me have some time to investigate on your case and I will get back to you with findings.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi,

Are there any error messages that you could provide to us as you can't interface the input/output with your custom verilog?

Best regards,

Zi Ying

[vmetodiev]

Hi Zi,

First of all, thank you for your help and immediate response!

Secondly, I do not have any technical issues with the programming environment. I am just trying to thoroughly understand what is happening behind the Quartus automation and how to build my custom Verilog logic on top of a generated IP core. Let's narrow the scope of my question to the Ethenet IP core only.

Up to this point, I've managed to understand where the instantianted IP core spanws its files and locate the Top.v module. Now, in order to use Ethernet IP core, the documentation suggests running several TCL test scripts - for packet generation, monitoring, etc. As mentioned above, my actual "issue" is that I am using something without knowing what is exactly happening under hood. And that bothers me way too much.

So, my next goal is to manually send and receive a single Ethernet frame by adding my custom logic to the Top module (attached). Could you please help me with:

1) Some example code?

2) [even better] Some idea how to "debug" what is happening behind the TCL scripts? Do they generate any Verilog code that I can then review and modify to understand how the Ethernet Top.v module is utilised?

Thank you in advance!

[vmetodiev]

I have moved my question in a new topic:

https://community.intel.com/t5/Programmable-Devices/Triple-Speed-Ethernet-Verilog-TX-RX-example/m-p/1429732#M87756

The moderator(s) may close this one.