Dear All,
we are using Cyclone 10 (10CX105YF780E6G) and
we have to implement an LVDS Receiver for 33 rx_in channels with only one rx_inclk at a data rate of 900Mbps.
So, we need at least 2 I/O banks and 2 LVDS SERDES instances.
How can we use the same rx_inclk for several LVDS SERDES instances with their I/O PLLs?
Can we use the Global clock network for the reference clock to the I/O PLLs?
Best regards,
Bohris
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Hello Bohris,
May I know which version of Quartus are your team using for this design?
Thanks.
We are using Quartus Prime Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition.
Hello,
I think 900 MHz desired inclock frequency is out of range.
Thanks.
Hello Bohris,
You can try do that on Pin Assignment tab.
Thanks.
The PLL inclock frequency of our design is 450MHz for a data rate of 900Mbps.
Reducing the LVDS Receiver SERDES to 8 rx_in channels with the PLL reference clock on the same bank as the data channels, the compilation is successful.
With more than 8 rx_in channels we want to use the PLL reference clock from another bank. Is this possible?
Hello Bohris,
I am sorry to tell you that that is not possible because IOs on each banks work independently. I hope you can work your design around this constraints.
Thanks.
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