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Bohris
Beginner
67 Views

Cyclone 10 use bank 2L for an LVDS clock input

Dear All,
we are using Cyclone 10 (10CX105YF780E6G) with an external memory interface (DDR3 Scheme 2, 800MHz).
DQS groups and RZQ are placed in I/O bank 2K, address/command in I/O bank 2L.
The DQS groups are using all the I/O lanes in I/O bank 2K and there is no spare differential clock input there.
So we have to place the PLL reference clock in I/O bank 2L.
Using an LVDS clock as PLL reference clock in I/O bank 2L, the fitter generates an error.
Are there any constraints to make it possible to use bank 2L for an LVDS clock input?

Best regards,
Bohris

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3 Replies
AminT_Intel
Employee
47 Views

Hello Bohris,

 

May I know what errors you the fitter generate after you use LVDS clock as PLL reference. 

 

Thanks.

Bohris
Beginner
35 Views

Hi,
with single ended PLL refclk (PLL reference clock I/O standard: SSTL-135) at PIN_F23 the compilation is successful.
Using LVDS (with or without On-ChipTermination) the following error occurs:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)).
Error (175020): The Fitter cannot place logic pin in region (38, 87) to (38, 88), to which it is constrained, because there are no valid locations in the region for logic of this type.
        Info (14596): Information about the failing component(s):
            Info (175028): The pin name(s): EMIF_REFCLK
        Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
            Error (179009): Could not find enough available I/O pin locations that supports the LVDS standard (1 location affected)
                Info (175029): pin containing PIN_F23
            Info (175015): The I/O pad EMIF_REFCLK is constrained to the location PIN_F23 due to: User Location Constraints (PIN_F23)
                Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

AminT_Intel
Employee
10 Views

Hello Bohris,

I am sorry to tell you that there is no condition that allows you to do that. Each I/Os in each banks work independently. The idea is that we want the fastest and shortest route for our IOs. Taking IOs from another bank will make it inconvenient and longer. I hope this answer helps.

Thanks