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Valued Contributor III
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Cyclone 10: definition of "POR time"

I am looking for the definition of "POR time". What does it mean? What happens at the beginning and at the end of the POR time interval? The term is used in the following context: 

 

"The MSEL pin settings determine the POR time (tPOR) of the device." (Cyclone 10 LP ... handbook) 

 

"The fast POR time is 3 ms < TPOR < 9 ms for a fast configuration time. The standard POR time is 50 ms < TPOR < 200 ms, which has a lower power-ramp rate." (AN-800, Cyclone 10 LP device design guidelines) 

 

"The maximum power supply ramp time for Cyclone 10 LP devices is 50 ms for standard POR or 3 ms for fast POR" (AN-800)
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Valued Contributor III
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Hi, 

 

The POR circuit keeps the device in a reset state until the power supply voltage levels have stabilized during device power up. 

After device power-up, the device does not release nSTATUS until VCCINT, VCCA, and VCCIO are above the POR trip point of the device. 

 

Using MSEL pin settings you can select either of one(standard/fast). 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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Hi Anand, 

 

What happens at the beginning and at the end of the POR time interval? 

 

In other words: What is the beginning of the POR time? And what is the end of the POR time? 

 

Best regards, 

Oscar
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Valued Contributor III
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--- Quote Start ---  

POR Specifications: 

 

Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration. 

--- Quote End ---  

 

 

Look for "POR Specifications" in (for example) the "cyclone® 10 gx device datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf)" 

 

Cheers, 

Alex
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Valued Contributor III
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Thanks a lot, Alex.

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New Contributor I
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Hi, Alex. Is there any specification about Tramp? Does it mean time interval between 10%-90% of nominal voltage of an FPGA power rail ?

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