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Cyclone 10GX: Watchdog timer reconfiguration detected as CRC error

Zak
New Contributor I
141 Views

Hello,

 

I'm using the "Remote Update Intel FPGA IP" on a Cyclone 10GX device.

Basically I want to check the cause of reconfiguration and I get "CRC ERROR" even if it's due to the watchdog timer. The same strategy works with Cyclone V...

 

A little overview of my system:

I have 2 bitstream images (factory and user) and 2 NiosII firmware (factory and user) which are loaded in sequence at startup.

So, the factory image is loaded from flash. The NiosII execute the factory FW and performs some preliminary checks on the hardware integrity. Then it trigger a reconfiguration of the FPGA in user image, specifing a watchodog timer of about 10s.
The user image loads and the user firmware start executing with no issues.
I've been using this architecture with Cyclone V for years without any issues.

 

If the user firmware locks for some reason (to test it I simply add a 30s usleep()), the FPGA reconfigure itself in factory image/firmware.

Here's the problem: I want to detect the cause of reconfiguration, and with Cyclone V I can correctly read "NCONFIG" at first startup, "WDTIMER" when the timer triggers or "CRC ERROR" when the user image is corrupted.

With Cyclone 10GX I see "NCONFIG" at first startup but I get "CRC ERROR" even if the cause of reconfiguration is due to the watchdog timer.

These are the FW instruction I'm using to check the reconfig condition:


altera_remote_update_state *ru_s;
ru_s = altera_remote_update_open ("/dev/remote_update_0");
alt_u32 ru_trig_cond = IORD_ALTERA_RU_RECONFIG_TRIGGER_CONDITIONS(ru_s->base);
if (ru_trig_cond & ALTERA_RU_RECONFIG_TRIGGER_CONDITIONS_CRCERROR)
{
// do something
}
if (ru_trig_cond & ALTERA_RU_RECONFIG_TRIGGER_CONDITIONS_WDTIMER)
{
// do something
}

 

Any idea why is this happening?

Thank you

 



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WZ2
Employee
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Hi there.,

I’d like to clarify something: do you mean that even when the reconfiguration is triggered by the watchdog timeout, the “Reconfiguration Trigger Conditions” bits in the parameters show 00001 instead of 10000?

Can this be confirmed through Signal Tap?

BR,

wz


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