We are using the Cyclone 10GX FPGA device 10CX105YF672I5G along with Micron make DDR3L device MT41K128M16JT-125 and Spansion make 16-bit NIOS compatible CFI Flash device S29GL256P10TFI010 in our design. Help us to find the appropriate pinouts for 16-bit Data and Address lines of the DDR3L device and the CFI Flash device to interface with the Cyclone 10GX FPGA device.
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First of all, can you separate this thread into two thread?
You can use this thread for the EMIF side.
The new thread should be for flash device.
The reason for that is for better support from Intel expert in each area.
In order to find appropriate pinouts, you may need to refer to Pinout file from this link:https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/cyclone-10/10cx105.xls
When you open the 10cx105.xls, you should refer to Pin List F672 which is a reference for the device that you used.
Please let me know if you have further question in this topic.
Thanks for your prompt reply.
I have already checked the pin list F672 of the 10cx105 pinout file. The DDR address lines/connections are not specified in it. And also, the DDR data lines/signals like DQ0, DQ1, ......... DQ15, have been assigned to multiple pins. How can we confirm the proper connection?
It's strictly specific when you're making pin assignment for the DDR.
You should choose which IO Bank that you want to use as the Address and Command pins and as the Data pins.
The Pinout file will provide the information for each pin of the device.
You will find which DQ group that you have to used for your Data pins.
I'm not sure on multiple pins assigned that you mentioned.
Can you provide the a snapshot of it?
You can confirm the pin connections that you have made by running the Fitter analysis.
From there you can see whether your configuration is right or wrong.
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