Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Cyclone 4 I/O pin configuration

Altera_Forum
Honored Contributor II
‎01-26-2011 05:25 PM
1,375 Views

I am using Cyclone 4 FPGA (ep4ce15) for my design. During the power ON all the I/O pin are getting pulled to high through internal pull up. is there any way , i can pull down all the I/O pin to ground or tristate at power on?

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Altera_Forum
Honored Contributor II
‎01-27-2011 08:34 AM
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No, you can only change the state of the pins after configuration.

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