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Honored Contributor I

Cyclone 5 DDR3 with PLL fed by global clock



I am having trouble getting a design with DDR3 to work. I am trying to get the auto-generated example project from the UniPHY controller to work. Device is 5CEFA2F23C8.  


Unfortunately, a mistake on the design was made where no clock was connected to a region adjacent to the PLL used with the hard DDR3 PHY. The only connected clock is on Bank 3B. 


Compiling the example project as is results in failure due to fitting (won't let the clock from 3B feed the PLL). If I add an ALTCLKCTRL module, I can distribute the clock to the PLL, and the design will compile and fit. However, the TimeQuest analyzer gives many errors, including worst case slack of -3626 ns! Running the EMIF toolkit, results in failure during calibration. 


I also get the message: 

Critical Warning: PLL clock if0|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid. 


Any ideas on how to salvage this without a board re-spin? Maybe something to add to the SDC to define the clock relationships? 


Many Thanks
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