Cyclone II Lock Up after 4 seconds

[Altera_Forum]

I have a Cyclone 2 EP2C5 design that will run for 5 seconds before the entire part freezes. Four out of five boards operated correctly after removing reset synchronization for the the 20MHz domain. However, very small changes in the design will result in failures again. Oddly, everything stops even though the Bus controller and I2C repeater do not interact with each other. Reset is brought in through the DEV_CLR pin with the device clear option turned off. The design only uses 16% or resources. Does anyone have any ideas on what would cause the part to lock up? 

 The design has three sections: 1. Proprietary Bus Controller (drawn with 74 series parts but has been working for several years in a FLEX10K device) running off 2 MHz clock  2. I2C repeater in VHDL running off of a 20MHz clock.  3. Pulse stretchers for LEDs (basically counters) running at 2 MHz and connected to the Bus Controller.

[Altera_Forum]

--- Quote Start ---  I have a Cyclone 2 EP2C5 design that will run for 5 seconds before the entire part freezes. Four out of five boards operated correctly after removing reset synchronization for the the 20MHz domain. However, very small changes in the design will result in failures again. Oddly, everything stops even though the Bus controller and I2C repeater do not interact with each other. Reset is brought in through the DEV_CLR pin with the device clear option turned off. The design only uses 16% or resources. Does anyone have any ideas on what would cause the part to lock up?  The design has three sections: 1. Proprietary Bus Controller (drawn with 74 series parts but has been working for several years in a FLEX10K device) running off 2 MHz clock  2. I2C repeater in VHDL running off of a 20MHz clock.  3. Pulse stretchers for LEDs (basically counters) running at 2 MHz and connected to the Bus Controller.  --- Quote End ---    Hi,  did you use signaltap, in order to observe internal signals ? If yes, can look whether all regsiters are set to "0" ? Why are using the DEV_CLR pin for the reset ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Why are using the DEV_CLR pin for the reset ?  --- Quote End ---   I understand, that DEV_CLR is used as a regular pin.  I think, the problem is either hardware related, e.g. supply voltage drop, or must be searched in the logic design.