Cyclone II and DDR pins

[Altera_Forum]

Hi 

 In Cyclone II ep2c5 pinouts document: http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf Some pins have additional discription: DQxxx DQSxx DMxx.  Why this DDR signals are assign to this pins? Is that requisite assignment or only recommended? If recommended then why?  PGW

[Altera_Forum]

I found information that DQS signals are assign to this pins because this pins are routed directly to the clock control block and global clock bus. 

 But I still don't know why DQx (data) and DM (data mask) signals are assign in this way.  This assignment is not comfortable for me but I don't know whether I can change it.  Any suggestion will be appreciate.  PGW

[Altera_Forum]

You need to assign DQS/DQ lines to special S/Q pins because the FPGA logic (usually the ALTMEMPHY) needs to adjust the clock phase at the input buffers in order to capture the data correctly. Only S and Q pins have this capability. 

DM lines, which are outputs (and all the other DDR lines for this matter), can be assigned to any pins as far as I am aware.

[Altera_Forum]

--- Quote Start ---  You need to assign DQS/DQ lines to special S/Q pins because the FPGA logic (usually the ALTMEMPHY) needs to adjust the clock phase at the input buffers in order to capture the data correctly. Only S and Q pins have this capability. DM lines, which are outputs (and all the other DDR lines for this matter), can be assigned to any pins as far as I am aware.  --- Quote End ---    Thanks for response.