Cyclone III EP3C120F780C7 @ 150MHz?

[Altera_Forum]

Hi, 

 I am designing a video processing system on a Cyclone III (EP3C120F780C7). The FPGA is expected to run at a clock of at least 150 MHz. Is there anyone has experienced a system that fast?  I need your responses to make decision.  TIA avtx30

[Altera_Forum]

I'm using a Cyclone II (EP2C50F672C8) and about 75% to 80% of it is running at over 147MHz so I'm sure that your Cyclone III can work at 150MHz though you might have to be a bit a careful with your design.

[Altera_Forum]

--- Quote Start ---  Hi,   I am designing a video processing system on a Cyclone III (EP3C120F780C7). The FPGA is expected to run at a clock of at least 150 MHz. Is there anyone has experienced a system that fast?   I need your responses to make decision.   TIA avtx30  --- Quote End ---     There are some of the Altera reference designs for Cyclone III which are near to the speed you have quoted: 1. 122.88 MHz: http://www.altera.com/support/refdesigns/sys-sol/wireless/ref-wcdma-ducddc.html 2. 100 MHz: http://www.altera.com/support/refdesigns/sys-sol/indust_mil/ref-des-secur-mem.html   The embedded multipliers in Cyclone III devices can operate at 260 MHz. There is a white paper on "Using Cyclone II FPGAs for Wireless Applications" (http://www.altera.com/literature/wp/wp-01017.pdf) which has reference to using these FPGAs in the range 144-203MHz.

[Altera_Forum]

Your fmax will depend heavily on your design. Best thing to do is some test compiles with your code and see what results you get. 

 Jake

[Altera_Forum]

Thanks for useful info. > all 

 @Jake It's me again who asked about DDR2 controller at another thread. My problem is, I have to output a 1080p60 video with pixel clock of 148.5MHz (according to the HDTV standard). To achieve this, the simplest way is to process video data at a clock of 148.5MHz (150MHz).  From responses in this thread, I feel that 150MHz is a big challenge. I have to think about other solutions. Would you please tell me about yours: Have you ever output 1080p60 video using Cyclone III? How did you achieve that? Did you designs include any vendor's IP (such as Altera's VIP)?  I will use Altera's Frame Buffer (comes with the VIP suite v8.0) as a 1080p60 video frame buffer. Its Avalon MM master's data width is 128 (interfaces with a DDR2 SDRAM controller) while its Avalon ST Source/Sink's data width is 24 (8-bit R,G,B parallel). How do I configure the Frame Buffer so that it can make use of 128-bit data buffering? If this were ok, I would process video data at clock of about 100MHz but still have pixels output at 148.5MHz?  Sorry for asking many questions. I am relying heavily on all of you.... Thanks.

[Altera_Forum]

I unfortunately have not used Cyclone III at all. I am currently doing 1080p60 video with the 148.5MHz parallel clock but my design is a Stratix II GX. 150MHz is a walk in the park for that family. 

 Now in your case, I would not try to run your video processing clock at less than 148.5MHz. You might be able to go a little less than that but not much. I'm pretty sure you can hit the 148.5MHz target in the cyclone III.   As far as the frame buffer goes... Configure the frame buffer just as you have said. Match the width of the frame buffer's memory interface to match your DDR2 memory controller interface width. So for example, if you've got a 64-bit physical width memory (size of a DIMM), your normal local interface width to the DDR2 High-Performance controller would be 128 bits. However, the High-Performance controller also gives you the option of running the local interface at half the clock frequency and twice the data width (so 256 bits). The tradeoff is obviously the wider bus. Anyway, let's assume that you are going to use the full-rate interface rather than the half-rate. So you've got a 128-bit interface to the DDR2 controller.  You would configure the frame buffer as shown in the attached image.  Now there is an undocumented change you can make to the frame buffer that will allow you to run your video input and output on one clock and the memory interface on another.  Edit the file: C:\altera\80\ip\frame_buffer\lib\vip_vfb_hwfast.hpp  Change line 13 from # define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK false to # define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK true  Now when you create the Frame Buffer component in SOPC builder, your avalon streaming interface and avalon memory masters will be on different clocks. Connect the streaming interface to your video processing clock and the memory masters to the DDR2 controller interface clock.  This will allow you to run the memory interface at something less than 148.5 MHz.  What the frame buffer is going to do is write/read several 24-bit pixels to/from the memory in parallel.  Jake

[Altera_Forum]

Hi Jake, 

 I don't see an attachment, would you send it again or send it to my email address <avtx30@gmail.com> ?  I will reply later. It's time for me to go to work....  You are going to save my life....

[Altera_Forum]

I've edited the previous post to add the attachment. Sorry, The forum apparently doesn't like Firefox and I had to convert it to PDF because of the resolution restriction for images. 

 Jake

[Altera_Forum]

Thanks Jake et. al 

 I will try separate clocks for the sdram masters with video processing clocked at 148.5MHz. Report later.  Bests regards