Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Cyclone III & EPCS16 configuration / DCLK signal

Altera_Forum
Honored Contributor II
‎09-29-2011 02:38 PM
1,121 Views

I have a question about the configuration of a Cyclone III with a EPCS16 in AS mode. 

I have 8 prototype boards for development. JTAG program debugs OK. The POR configuration fails on 2 boards and intermittent on another 2. The solution is to place a 22pF cap on the DCLK at the EPCS device (I discovered this while using my scope probe). 

 

I am using Standard Speed AS. 

The EPCS is at 3V3, the MSEL pins are at 2V5. 

 

It is an 8-layer board with ground and power plane, but could this be poor routing / layout problem? 

The trace is 30-40 mm max. 

 

Are there any obvious things to look out for / have others had similar? 

 

Regards 

Konrad
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎03-31-2015 05:46 PM
415 Views

I am seeing this problem now. Anyone else see this. My concern is that the ALTERA documentation says a maximum of 15pf on the DCLK pin, what can this really be?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.