Cyclone III VCCA current?

[Altera_Forum]

I power 4 PLLs of a Cyclone III VCCA with a 50mA LDO regulator. I only use 1 PLL. 

What current should I supply? 50mA should be fine? I can't find details of the VCCA consumption in the datasheet.  I have a PLL lock problem. The PLL seems to be losing lock intermittantly. I am pretty sure this is poor layout. The VCCA tracks are 0.1mm. I feed the VCCD_PLLx pins via a ferrite, 10u 100n and 22p but all caps are placed at the edge of the device and the feed is then 0.1mm.  The PLL falls over when the IO pins (an external data bus at 3V3) are most active.    Regards Konrad

[Altera_Forum]

If you enable PowerPlay in your project settings (and have set up the correct clock frequencies in your timing constraints), you will get a powerplay report that lists the estimated supply currents on all inputs, including VCCA. But I agree that using 0.1mm tracks for that purpose isn't the best layout method. The recommended way is to use power planes, but in practice decently wide rectangles from your decoupling capacitors to the power pins can be enough. 

Is your PLL clock input in the same I/O bank than your toggling external data bus? In that case it could also be noise induced by the bus, or bouncing in the VCCIO power supply in that bank that could cause the PLL to loose lock. In the PLL megawizard, there is a bandwidth setting. Try to put it to "Preset Low" instead of auto and see if it gets better. If not you may need a new layout round for your board.

[Altera_Forum]

Thanks, 

the PowerPlay tells me 35mA, so I'm OK I had already set Preset Low in the megawizard, monitoring the power supplies VCCA and VCCD_PLL - I could see no glitches - I tried adding 2 x 100n caps (0402 to the bottom of the BGA!) to no affect  I think I have finally solved it with a 22R resistor in series with the 40MHz oscillator. It looks like poor routing of the clock on the PCB.  Thanks again for the advice