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Hi All,
I have been following all the threads relating to modifying the boot loader code to allow dual factory and user FPGA and NIOS applications to exist in EPCS. There was loads of good info, especially from JacobJones on this thread http://www.alteraforum.com/forum/showthread.php?t=20623 (http://www.alteraforum.com/forum/showthread.php?t=20623) So, an obvious cheeky question, has anyone actually modified JJs Stratix II code to work on a Cyclone III. I am after exactly the functionality that JJ proposed. I'm a big fan of reuse!!! If anyone has this code that they are willing to share it would be appreciated. If not then it's time to dig out the NIOS assembler manual and Remote Update Controller datasheet! Thanks in advance VernLink Copied
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I think you might want to have a look at AN-458, on Altera's AN page (http://www.altera.com/literature/lit-an.jsp). Since you're likely going to be using a larger onchip memory to handle this sort of thing, you might want to have a look at the simple C-based EPCS bootloader that I wrote some time ago (attached).
Go ahead and post further questions to this topic thread and I'm sure either Jake or myself (or others) will chime in with decent/relevant info... Cheers, --slacker (aka Brendan)- Mark as New
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Thank you so much for you code
I have some trouble reading your code In line 16 in the comment you mentioned that EPCS flash offset is 0x700000, where did that come from? And also in the read section of your code for example line 23, where do you copy the read data? In my scenario I have multiple NIOS II processor and I want my top processor to read the data from EPCS and write that data to the other NIOS II processor reset vector which is SDRAM memory and start executing I believe I can modify your bootloader for my use Please give me some suggestion
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