Cyclone III configuration problem

[Altera_Forum]

Hi I am using EPCS16 to configure Cyclone III EP3C25E device in AS mode. I load the pof configuration file into EPCS16 using external Speedpro 3000A third party programmer (JTAG is not used at all). VCCIO for bank 1 and VCC for EPCS16 are all 3.3v. MSEL pins are 010 and MSEL1 is connected to 2.5v VCCA. I disable JTAG by connecting TDI and TMS directly to VCCIO 3.3v and TCK directly to ground (TDO floating).  

 What I observed from my pcb is that nsc, nstatus and conf_done are always low. nconfig is always high. Data and Dclk have about .8v stable voltage. All the I/O pins (defined and not used) have around 1v voltage. Can anyone please tell me what could cause the configuration problem? Thanks.

[Altera_Forum]

Did you connect the exposed pad to GND? Did you provide all necessary pull-up resistors shown in the AS configuration schematic?

[Altera_Forum]

I connect the pad to GND and all the pull up resistors. What I am confused is that nstatus never get pulled up to high and nconfig is always high. It seems like that the EPCS16 is never enabled.

[Altera_Forum]

Some of the observations sound confusing. E.g.: An unconfigured FPGA has weak pull ups on all standard I/Os. You should measure respective VCCIO rather than 1V at these pins (with an usual oscilloscope probe or a digital multimeter). Even 0.8 V for AS pins isn't a normal voltage, cause these pins should be driven either high or low in AS mode, as long as nCE is pulled low as required. 

 The configuration in EPCS may be invalid, but you should at least observe an initial configuration sequence. Low nStatus indicates POR state, usually. As clarified in the datasheet, one of the startup condition may be missing, correct core voltage or VCCA. You also should check nStatus pullup and possible pin shorts at the board.

[Altera_Forum]

I have got all the I/Os having 3.3v voltage now. But the configuration is sitll incorrect. The nconfig pin stays high all the time and nstatus, conf_done and ncs always stay low. I did not even see a clock toggling at the DCLK pin. Can someone plz tell me what could cause the problem? I double check the ground plane of the FPGA and have it connected to the ground pins.

[Altera_Forum]

The external conditions for releasing POR are described in the hardware manual. If nSTATUS is low, although it has a correct pullup, I would expect POR condition. 

  --- Quote Start ---  The POR circuit keeps the device in reset state until the power supply voltage levels have stabilized on power-up. Upon power-up, the device does not release nSTATUS until VCCINT, VCCA, and VCCIO of banks 1, 6, 7, and 8 are above the device’s POR trip point. On power-up, VCCINT and VCCA are monitored for brown-out conditions.  --- Quote End ---   A JTAG interface would be generally helpful in further clarifying the issue.