Cyclone III device utilization issues

[Altera_Forum]

I am having trouble getting my design to finish compiling. I think it is using about 50% of the device. It doesn't error out, it just runs forever. Has anyone else had a problem with this? How much utilization can you usually get out of a Cyclone III? I am running at 50 MHz clk, and have a 125 MHz clk on the Ethernet and DDR2 cores.

[Altera_Forum]

The fitter shouldn't run forever. From a compile-time perspective, the worst case scenario is a design that fits during placement but is really hard to route, in which case it spends a lot of time in the router and will then go back to re-trying placement with an emphasis on routing. It's a very special condition that seldom happens, and Cyclone III has lots of routing, so should almost never happen there. And if you're 50% full, it definitely won't happen. Are you getting messages? If not, what's the last one? What does "forever" mean?

[Altera_Forum]

I let it run while I was on vacation for a week and when I got back it was still running. It gets stuck at the Fitter(place and route) step at 80% completion. I don't get any errors if that is what you mean. I do get a message that says it has been running for x hours. It gets to the same place Fitter(place and route) 80% if I let it run overnight. I tried running it with the compiler options turned down, and it did finish in about 20 min in the lowest setting, but it didn't meet timing. If I run it in the med setting where it will make it meet timing and perform no more optimizations I sill get the long compile time.  

 I had added several Ethernet cores (7) to try and make the design bigger. I think this could be causing my problem because when I did the failed timing run, the part that failed was the 125 MHz clk. In my real design I intend to only use 2 Ethernet cores.   I am trying to figure out how much utilization you can practically get out of the device so I can plan my required margins. This is the first time I am using an Altera device and so I am trying to establish a good rule of thumb for utilization throughout the design process. Do you know of an example design that is quite large?

[Altera_Forum]

Something is wrong, as it should never run off into the weeds like that. What compiler options are you modifying? Is it physical synthesis? (This runs later in the fitter when you set it to Normal Effort, and I'm guessing some analysis algorithm is getting lost in the weeds or something like that.) As for utilization, what you're doing is much better than taking some random design, as all designs are different and will pack/fit differently. 

Perhaps take the ethernet core hierarchies, right-click and Locate to Assignment Editor, copy their name into the To column and make the assignment Netlist Optimizations = Never Allow. This basically disables Physical Synthesis on those hierarchies, and might get around your issue. (I'm assuming it's the Physical Synthesis you're talking about, but not sure).

[Altera_Forum]

The compiler option I am editing is in settings -> Fitter Settings -> under Fitter Effort the default is standard fit (highest effort), the lowest one that I said finished is the Fast Fit, and the one I am trying to use for real is the Auto Fit(reduce Fitter effort after meeting timing requirements). 

 I am using Qsys to build by project and am duplicating the Ethernet cores in there. When I right click on it there is no option for Locate to Assignment Editor, but I did find in Quartus II under Assignments -> Assignment Editor. I see that I can add a new line and see the option you said. I will try this and post back. I assume that I should type the name of the Ethernet hierarchic into the To field.

[Altera_Forum]

Don't worry about trying the Netist Optimizations = Never Allow. You're not changing Physical Synthesis, so that won't make a difference.  

I'm surprised Auto is taking so long. Perhaps try Standard. If that doesn't work, can you file an SR?

[Altera_Forum]

So It was set to standard when it went for 14 days. On Auto I let it run for 2 days. I will file an SR.  

 Just out of curiosity do you know how full can you usually get these devices?

[Altera_Forum]

90+%? There are two issues. One is that as devices fill up, the performance can get a little worse. If you barely meet timing, then it becomes an issue at a lower percentage. The other issues are when it barely routes or no-fits altogether. That should be above 90%. (And that's just logic, but memory and DSPs can also be overutilized...)