DDR Valid signal

[Altera_Forum]

So i am using the UniPHY DDR2 Controller to to store data. I am not using any SOPC component i am just using it as straight HDL. I am therefore stuck making my own Avalon Master to send to the Controller Avalon slave interface. So i set up a test to examine exactly how the controller acts and how i will need to use it. but i came across a weird problem. When i issue a read weather it be burst or not, sometime (randomly) the data Bus will get the correct data but the Valid bit dose not get asserted. Like i said it is really random and the data is there so the valid should go high. In the signal tap screen shot attached i am doing a burst read of size 2. you can see the data changing with the correct 2 data. But the valid signal only goes high on the second data. theoretically it should of gone high at -2 when the data was ready to be read. Like i said sometime it will do it properly but sometime it wont. So i am very puzzled on why it would do something like that. I also want to add that my signal tap as the same clock as the controller.