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Cyclone III max I/O frequency

Altera_Forum
Honored Contributor II
1,501 Views

Hi, 

 

I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a  

CylconeIII EP3C25(-8) 

 

I want to provide this clock on a pll output pin with SSTL 2,5V standard. 

 

In quartus II Version 7.1 I got this message: 

 

Warning: Clock period specified for PLL output clock "pcixp_to_wb_top:g1x125|pxpll_altera:px_pll|altpll:altpll_component|altpll_b7q1:auto_generated|clk[2]" must be greater than or equal to 4.761 ns for output I/O "px_txclk" 

 

Is it only possible to have 210Mhz on this output pin? 

 

What can I do to solve the problem? 

 

regards 

 

cyclone
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12 Replies
Altera_Forum
Honored Contributor II
257 Views

(I'm guessing that you are driving at 1.8V levels on a dedicated clock output). 

 

Have a look at : 

 

"Maximum Output Toggle Rate on Cyclone III Devices (MHz)" 

 

in here: 

 

http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf

 

You may have to use a higher speed grade.
Altera_Forum
Honored Contributor II
257 Views

Looking at the table in the PDF noted above you'll have to know whether it is a row, column, or dedicated pin like a PLL output pin. Also, which SSTL2 Class.

Altera_Forum
Honored Contributor II
257 Views

Thank you all for the good information. 

 

I´m using SSTL2 on bank 8 of the FPGA (pin B6). Speedgrade -8 Comercial type. 

 

This is a row I/O pin isn´t it?  

 

Looking at page 30 on the pdf I can see that the toggle frequency should be 280Mhz.  

 

Quartus told me tha only 210Mhz are possible! 

 

How could that be? 

 

what is the derating factor on page 33? 

 

regards 

 

Cyclone
Altera_Forum
Honored Contributor II
257 Views

 

--- Quote Start ---  

 

what is the derating factor on page 33? 

Cyclone 

--- Quote End ---  

 

See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model).
Altera_Forum
Honored Contributor II
257 Views

 

--- Quote Start ---  

See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model). 

--- Quote End ---  

 

 

OK. 

 

That shouldnt be the problem in my case because there is 0pF load specified in quartus. 

Due to this the max. frequency should be 280Mhz and not 210Mhz?:confused: :confused: 

 

I also tried speedgrad 6 and 7 and there is no problem :(
Altera_Forum
Honored Contributor II
257 Views

There are a number of possibilities: 

1) You haven't set SSTL_2 as you thought (double check) 

2) The timing model in Quartus may not be up to date with the latest product information (check with Altera) 

3) Something else we both don't understand (quite possible, contact Altera via your distributor or directly via the web-site support I would suggest)
Altera_Forum
Honored Contributor II
257 Views

 

--- Quote Start ---  

There are a number of possibilities: 

1) You haven't set SSTL_2 as you thought (double check) 

2) The timing model in Quartus may not be up to date with the latest product information (check with Altera) 

3) Something else we both don't understand (quite possible, contact Altera via your distributor or directly via the web-site support I would suggest) 

--- Quote End ---  

 

 

1) I have checked it again and the pin is set to SSTL2-CLASS I 

2) I also thought about that and I hope that that is my problem :D  

3) I also started a request to altera but I found out that the information in this forum (as you could see in this threat) is faster and there are also quiet good ideas! 

 

THANK you all 

 

:rolleyes:
Altera_Forum
Honored Contributor II
257 Views

To address your previous question on whether B6 in bank 8 is a column or row pin. Bank 8 is on the top left and from the I/O bank diagram in the pin table on page 14 it is shown as a column pin. 

 

http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf
Altera_Forum
Honored Contributor II
257 Views

 

--- Quote Start ---  

To address your previous question on whether B6 in bank 8 is a column or row pin. Bank 8 is on the top left and from the I/O bank diagram in the pin table on page 14 it is shown as a column pin. 

 

http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf 

--- Quote End ---  

 

 

hmmm... is that name convention because of row and column LE interconnection within the FPGA :confused: ?
Altera_Forum
Honored Contributor II
257 Views

Yes. Column pins connect to column interconnect. Row pins connect to row internconnect.

Altera_Forum
Honored Contributor II
257 Views

Hi, 

I think you 'd better make sure that you 've set Quaturs the righit conditon!
Altera_Forum
Honored Contributor II
257 Views

which condition do you mean?

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