Cyclone III problem with USB blaster JTAG communication

[Altera_Forum]

Hi all 

 I've spent the last week debugging the jtag connection between the fpga and the usb blaster.:mad:  I finally found something that is wrong.:) In JTAG there are 4 signals.. The first 3 signals TCK, TMS and TDI works correctly. I've checked them all with a scope.  Now if I disconnect the TDO wire from the FPGA to the usb blaster and monitor this signal coming out of the FPGA with the scope it looks perfect. The egdes are nice and no bad overshoot or anything like that.  And the signal goes up to 3.3 volt which is to be expected as VCCIO for bank 1 is 3.3V  Now if I connect the wire to the usb blaster (rev C) then the signal stil looks good in terms of wave form but only goes up to 1.5Volts.  The usb blaster revC specification tells me that the usb blaster needs 1.8Volts in order to actually read the signal as a 1. So it makes sense that it doesn't read the 1.5Volt signal and nothing happend.. Error: can't scan JTAG chain.  I've measured the input resistance on the USB blaster between ground and the TDO input pin.. 74Ohm. Working on 2.5Volt this means the FPGA must drive more than 30mA. The FPGA specification if I understood it correct specifies something around 8mA drives strength for JTAG.:confused:  So it seems.. that I have a usb blaster that is incompatible with the fpga which it has been made for. Which is offcourse impossible since both has been made by altera.:eek:  The only solution I see currently is to put in a buffer between the FPGA and usb blaster so that the fpga don't have to drive the usb blaster directly. Hopefully this does not destroy the signal timing.  But please if anybody can give me some help as to why this is happening in the first place? I've already contacted my local field engineers from the distrubutors in my country and they don't seem to have a clue as to why this is happening.  Yes I've checked all the power supplies multiple times. I've even made sure there are not glitches on the power rails during JTAG communication. I've attached the JTAG USB blaster to external 2.5Volt so that it does not pull down the 2.5Volts on the board. I've tried a 3.3K pull-up on the TDO pin to 2.5Volt All the other connections for the EPCS chip has been verified multiple times. Other JTAG pullups and pulldowns are 1K to GND and 2.5V as in the fpga specifications. MSEL pins have been set to 010 directly to 3.3V and GND.  I've verified many other things I can't even remember anymore. All indicates that everything is working correctly... accept that the usb blaster seems to clamp down on the TDO signal and then can't read it.  Help is appreciated

[Altera_Forum]

I would like to assume that this is an individual defect of your USB blaster. Could you try to verify that by exchanging the blaster with that one of a collegue or friend? And, second idea, have you checked the target voltage on pin 4 of the connector? This pin powers the voltage converters inside the blaster.

[Altera_Forum]

We have only one other usb blaster available.  

And it is from terassic - it claim to be 100% compatible. But with it I see absolutely nothing. I think its completely broken.  I've checked the voltage on pin 4 on the pcb and its constant at 2.5Volts. Have not yet checked it inside the usb blaster.

[Altera_Forum]

Harald has basically answered the question. As an additional remark, TDO input at USB Blaster or any other JTAG interface is supposed to be high impedance and should never short the signal in a way you described. I expect that the PIV3T3254 level converter inside Terasic USB Blaster is defective or a solder short exists inside the adapter.

[Altera_Forum]

--- Quote Start ---  Hi all  I've spent the last week debugging the jtag connection between the fpga and the usb blaster.:mad:  I finally found something that is wrong.:) In JTAG there are 4 signals.. The first 3 signals TCK, TMS and TDI works correctly. I've checked them all with a scope. ---lines deleted--- Help is appreciated  --- Quote End ---    Heinrichdutoit, I am having a similar issue. Did you find a definitive solution for your problem?  Thanks, Craig

[Altera_Forum]

Hi, 

It looks like for some reason (bug) TDO and TDI signals are swooped on J4 pin header (Cyclone III FPGA Starter Kit). Again there are no pull-up resistors on TCK, TMS and TDI on the same cyclone III board. In provided schematics for Cyclone III FPGA Starter Kit (sheet 8) when you track nets  CIII_TCK, CIII_TMS, CIII_TDI and CIII_TDO to "TOP LEVEL" (Sheet 3) you can see  nets CIII_TCK and CIII_TMS are not connected there.  Best Regards

[Altera_Forum]

The previous discussion wasn't related to any Altera Dev Kit, as far as I understand. 

 However, I don't think, that the signals at CIII Starter Kit are connected wrong. The signal naming is somewhat confusing (different from other schematics). Regarding JTAG chain continuity, you have also to consider the HSMC JTAG connection. I actually don't see P/U and P/D resistors, minimal resistors are provided at the FPGA internally, mainly TCK may need a lower resistance P/D to prevent from configuration failure on some boards that have strong crosstalk.  I'm referring to the CIII_Starter_Kit-v7.2.0 doc from Altera FTP, you possibly have a different schematics, cause the page numbering seems to be divergent.

[Altera_Forum]

Hi 

 Ok so I solved the initial issues. It turns out both the blasters I had was broken or something. So we ordered 2 more. Both are Terasic blasters that we got from altera distributors.  In anycase things worked fine with the new blasters for some time now and I tested and compiled and uploaded many different programs to the board without problems.  But now once again things are broken.  We have 2 boards with different problems.  On the one board the TDI pin goes and sits at a voltage of 1.5Volts rather than 2.5Volts as the pullup suggested. If we lift the FPGA pin the problem goes away. On the other board the input impedence on the TCK pin went down to 1.x ohms. Meaning the TCK cannot be driven any more.   I can find no real reason for these problems accept apparently static. Its not like we have handled the boards alot. What I find disturbing is that my FPGA's seem to die on me one by one :( And then we have JTAG pins connected directly to a header that sits in the open which is apparently not staticly protected.  The one board worked fine yesterday and today it doesn't any more. So somehow it broke itself overnight. So only thing I can assume is that something that was statically charges touched the pin.  I'm considering putting on either a buffer or some clamping diodes of some sort to try and protect these pins. Can't afford losing alot more FPGA's this way.

[Altera_Forum]

this might explain our FPGA device are failing... 

http://www.altera.com/literature/es/es_usb_blaster.pdf

[Altera_Forum]

thank you for your reply. 

But that is complete opposite of our previous problems. With us the fpga fails completely and not the usb-blaster.  One of the preventive action we are taking is to leave the usb blaster attached to the 10-pin jtag header. This way avoiding any static charges forming on the jtag header while handling it.  So far neither fpga or blaster gave any problems. Although normally we switch of the board(fpga) before unplugging the usb cable.

[Altera_Forum]

As an additional remark, Terasic USB Blaster is using a different JTAG driver circuit. The said Errata Sheet doesn't necessarily apply to it.  

 As a general solution, some kind of protection should be provided for the JTAG port, e.g. schottky clamps to GND/VCCIO with small series resistors.

[Altera_Forum]

Hi, 

 Us is the same... we got 10 of 2500/ea dollar board with two fpgas... The failure happens when we remove the usb cable of the usb byteblaster while it is plug to a powered FPGA board... This sometimes short the FPGA jtag lines and we have two ocassions that the byteblaster fails and when tried using the faulty blaster to other board it consequently kills the fpga device wherever it is attach to... our preventive action is before connecting blaster to the powered fpga board we detect that the blaster will lit whenever we press the hardware button on the flash or quartus programmer this assure that the blaster is always power and configured..  The usb blaster errata is the closiest issue that i can relate the root cause of the problem...   rgds,  lanz

[Altera_Forum]

Bad indeed. Did you observe this behaviour with an original Altera (if so, which hardware revision printed on the enclosure?) or a Terasic USB Blaster? 

 With 100 ohm series resistors for the four JTAG lines, I remember to have observed excessive current consumption of the USB Blaster in some situations, but no permanent damage at any side.

[Altera_Forum]

we have rma'ed two byte blaster altera/terrasic... the altera is rev.c.... I remember I have put series ressitor on the jtag lines which are about 22 ohms.. maybe replacing it to 100 ohms might lessen this unwanted failures... Dont you have any problem proggraming/debugging thru jtag with this values of series resistor?... 

 rgds, Lanz

[Altera_Forum]

I'm using these resistors in conjunction with BAS40-04 schottky clamps at the FPGA pins, and JTAG is working without any problems. Of course, it may be a matter of chance, that I never experienced a hardware failure with plug/unplug of powered USB Blaster.