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Cyclone IV DDR2, mem_clk[0] placement error

Altera_Forum
Honored Contributor II
‎10-01-2013 07:48 PM
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Hi All, 

 

I'm using a Cyclone IV EP4CE40F484, implementing a 32bit DDR2 interface using banks 3 and 4 (bottom two banks). Banks 3 and 4 are 1.8V, all other banks are 3.3V.  

 

Is there a solution to placing the mem_clk[0] and mem_clk_n[0] signals in either banks 3 or 4 that does not result in the DDIO LAB placement warning? I can't seem to find one. 

 

Also curiously DQ4B and DQ2B groups only seem to have 9 DQ pins available, whereas DQ3B and DQ5B have 10. Since one has to be used for the DM signal that only gives 8 data bits for DQ4B and DQ2B making parity implementations a little tricky. Is this a typo in the docs, or a real restriction? 

 

Also does anyone have any links on how to use the 'wraparound' feature? Potentially this could be used to force two DQ pins into the other bank and possibly fix the clock issue but I can't find any documentation on how to implement or constrain it. 

 

Thanks for any help. 

Mark.
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