I am using the EP4CE40 FPGA with EPCS128 configuration device, and having problem on power up. What happen was it used to power up fine. But after I made some changes to my code and compiled, the FPGA cannot complete the configuration phase. When I use the previous image to flash the configuration device, the FPGA power up fine. How can the compiled logic design can affect the FPGA power up. I tried both Quartus 15.0 and 20.1.1. Both failed the same way.
Thanks for the reply.
Monitoring the nStatus and nConfig is my next step. Our board is small and those signal are hard to get to. Here are the steps we tried:
1. Program the FPGA with sof file through JTAG - result, FPGA works fine.
2. Program the Configuration Flash with jic file through the FPGA with JTAG - result, FPGA no startup properly. Please note that the programming of the Configuration Flash was completed and verified successfully.
Thanks for the update. It looks like your image is working fine. Just that there might be some issue when it is trying to programmed the FPGA from the flash where there is some issue. May I know how do you convert the JIC file?
Here are some update on this issue:
We have added the following two components as an alternate part for EPCS128 that used on this board due to obsolescence:
- Intel EPCQ128ASI16N
- ST-Micro M25P128-VME6GB
We tested them on the board with the release FPGA image and they work fine.
However when we made some changes to the FPGA code and release a new image, the problem started to show up. And failure is intermittent, some boards work and some don't.
Attached is the cof file for converting sof to jic.