Cyclone IV GX bank 9 VCCIO

[Altera_Forum]

Just wondering if anyone can help.. 

 I'm using a 4CGX150 with the JTAG pins (TDI, TDO etc.) dedicated to the usual 10 pin connector for JTAG programming. These pins are not used for any other IO, just the JTAG. I have Pin 4 of the 10 pin connector and the pull ups on TMS & TDI tied to +2.5V. But since the VCCIO power for the JTAG circuitry comes from Bank 9, what should the bank 9 VCCIO pin be connected to, +2.5V or +3.3V ?? There are no other devices in the JTAG chain.

[Altera_Forum]

--- Quote Start ---   I'm using a 4CGX150 with the JTAG pins (TDI, TDO etc.) dedicated to the usual 10 pin connector for JTAG programming. These pins are not used for any other IO, just the JTAG. I have Pin 4 of the 10 pin connector and the pull ups on TMS & TDI tied to +2.5V. But since the VCCIO power for the JTAG circuitry comes from Bank 9, what should the bank 9 VCCIO pin be connected to, +2.5V or +3.3V ??   --- Quote End ---  You can connect the bank VCCIO to 2.5V, and connect the JTAG connector pin 4 also with 2.5V. This will ensure the USB-Blaster drives 2.5V logic.  That being said. I never like to expose FPGA signals directly to the outside world, where an ESD event could damage something as critical as the JTAG pins. I personally prefer to have the JTAG pins buffered using voltage-tolerant TinyLogic devices, with series resistances, eg. see p44, and pp77-79  http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)  It doesn't add much cost, but it adds peace of mind.  The JTAG chain in the above schematic has a mixture of 3.3V and 2.5V signals. The LEDs in the chain are driven by 3.3V buffers, so that their Vf is met under all conditions (the LEDs are red while the FPGAs are powered, but not configured).  p261 of the Cyclone IV handbook has the comment:  "For multiple devices in a JTAG chain with the 3.0-V/3.3-V I/O standard, you must connect a 25-ohm series resistor on a TDO pin driving a TDI pin"  In your case, if you decided to insert TinyLogic devices in your JTAG chain (between the header and FPGA), you could power them at 2.5V. If you do not use these buffers, at least include a series resistor to provide some ESD protection for the FPGA ...  TinyLogic data sheets: http://www.fairchildsemi.com/ds/nc/nc7wz16.pdf http://www.fairchildsemi.com/ds/nc/nc7sz125.pdf  Cheers, Dave

[Altera_Forum]

Thanks Dave for an excellent and detailed reply. 

Yes I'm aware of the ESD issues, I have series resistors in line to the device. I sometimes add a DALC208SC6 device to absorb any stray static. The tiny logic is a good suggestion, but I have the board layout complete, so next time. I was more concerned about the VCCIO voltage, so I will go with +2.5V on pin G4 (VCCIO Bank 9) of the device.

[Altera_Forum]

--- Quote Start ---   Yes I'm aware of the ESD issues, I have series resistors in line to the device. I sometimes add a DALC208SC6 device to absorb any stray static. The tiny logic is a good suggestion, but I have the board layout complete, so next time.   --- Quote End ---    I prefer the TinyLogic parts rather than just ESD diodes, as they protect against an invalid voltage on the JTAG pins, eg. a 5V logic value from a non-standard JTAG programmer.    --- Quote Start ---   I was more concerned about the VCCIO voltage, so I will go with +2.5V on pin G4 (VCCIO Bank 9) of the device.  --- Quote End ---    I had a further look at the handbook, and did not see any problems with using 2.5V for the JTAG.  Cheers, Dave