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Altera_Forum
Honored Contributor I
788 Views

Cyclone IV GX transceiver eval board ethernet issue

Hi, 

I am trying to implement ethernet protocol using Cyclone IV GX transceiver starter kit and I am running into few issues. I am not using the triple mac ip core. 

first thing, I was able to configure the 88e1111 chip to disable the auto negotiation and set the rate to 1Gbps. After this I was able to see the data from the PHY as BC 50 BC 50 .....which tells me the PHY is in idle state. It was sending auto negotiating pattern before I configured PHY. 

When I sent pin command to the board, I can see the Rx LED blinks as long as I send the ping command, but I don't see the data changing on the receiver. PHY still sends the same idle pattern even when I send the ping command. Am I missing something? Do I need to send some information to PHY from FPGA, so that it can initiate the bit transfer. It would be great, if someone can help me with this 

 

Thanks, 

Ramakrishna
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Altera_Forum
Honored Contributor I
33 Views

I was able to get the data through 88e1111 to fpga. I had to send the same data pattersn BC 50 BC 50 ......to the PHY to make sure fpga is not idle state. Once I did this, I was able to see the data packet from the computer in signaltap. Only thing was when I was sending BC 50 BC 50....pattern I had to make sure I made the tx_control high when I send out BC so that the transceiver knows to encode it as a control word as opposed to a data word

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